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amd alchemy? au1000? processor data book - preliminary amd alchemy? au1000? processor data book september 2005 publication id: 30360d
2 amd alchemy? au1000? processor data book - preliminary ? 2005 advanced micro devices, inc. all rights reserved. the contents of this document are pr ovided in connection with advanced micro devices, inc. (?amd?) products. amd make s no representations or warranties with respect to the accuracy or completeness of the contents of this publication and reserves the right to make changes to s pecifications and produ ct descriptions at any time without notice. no license, whet her express, implied, arising by estoppel or otherwise, to any intellectual property rights is granted by this publication. except as set forth in amd?s standard terms and conditions of sale, amd assumes no liability whatsoever, and disclaims any express or implied warranty, relating to its products including, but not limited to, the implied warranty of mer- chantability, fitness for a particular purpose, or infringement of any intellectual property right. amd?s products are not designed, intend ed, authorized or warranted for use as components in systems intended for surgical implant into the body, or in other applications intended to support or sustain life, or in any other application in which the failure of amd?s product could create a situation where personal injury, death, or severe property or environmental damage may occur. amd reserves the right to discontinue or make changes to its products at any time without notice. trademarks amd, the amd arrow logo, amd alchemy, and co mbinations thereof, and au1000 are trademarks of advanced micro devices, inc. mips32 is a trademark of mips technologies. microsoft and windows are registered trademarks of mi crosoft corporation in t he united states and/or other jurisdictions. other product names used in this publication are fo r identification purposes only and may be trademarks of their respective companies.
amd alchemy? au1000? processor data book - preliminary 3 contents 30360d contents list of figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 list of tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.0 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1 1.1 product description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 1.2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.0 cpu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.1 core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.2 caches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.3 write buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 2.4 virtual memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 2.5 exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 2.6 mips32? instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 2.7 coprocessor 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 2.8 system bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 2.9 ejtag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 3.0 memory controllers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 3.1 sdram memory controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 3.2 static bus controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 4.0 dma controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 4.1 dma configuration registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 4.2 using gpio as external dma requests (dma_reqn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 4.3 programming considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 5.0 interrupt controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 5.1 interrupt controller sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 5.2 register definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 5.3 hardware considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 5.4 programming considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 6.0 peripheral devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 6.1 ac97 controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 6.2 usb host controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 6.3 usb device controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 6.4 irda . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 6.5 ethernet mac controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
4 amd alchemy? au1000? processor data book - preliminary contents 30360d 6.6 i2s controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 6.7 uart interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 6.8 ssi interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 7.0 system control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 7.1 clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 7.2 time of year clock and real time clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 7.3 general purpose i/o and pin functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 7.4 power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 8.0 power-up, reset and boot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 8.1 power-up sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 8.2 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 8.3 boot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198 9.0 ejtag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 0 9.1 ejtag instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 9.2 debug exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 9.3 coprocessor 0 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 9.4 ejtag memory range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 10.0 signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216 11.0 electrical and thermal specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234 11.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234 11.2 thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235 11.3 dc parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236 11.4 ac parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238 11.5 power-up and reset timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249 11.6 asynchronous signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252 11.7 external clock specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252 11.8 crystal specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253 11.9 system design considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254 12.0 packaging, pin assignment and ordering information . . . . . . . . . . . . . . . . . . 256 12.1 mechanical package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257 12.2 pin assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259 12.3 ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269 appendix a support documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271 a.1 memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271 a.2 databook notations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278 a.3 data book revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279
amd alchemy? au1000? processor data book - preliminary 5 list of figures 30360d list of figures figure 1-1. au1000? processor block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 figure 2-1. au1 core diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 2-2. cache organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 figure 2-3. au1 write buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 2-4. system bus arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 figure 3-1. sdram typical read timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 figure 3-2. sdram typical write timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 figure 3-3. sdram refresh timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 figure 3-4. static memory read timing (single read followed by burst) . . . . . . . . . . . . . . . . . . . . . . . 61 figure 3-5. static memory read ewait# timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61 figure 3-6. static memory write timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 figure 3-7. static memory write ewait# timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62 figure 3-8. one card pcmcia interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 figure 3-9. two card pcmcia interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 figure 3-10. pcmcia memory read timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 figure 3-11. pcmcia memory read pwait# timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 figure 3-12. pcmcia memory write timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 figure 3-13. pcmcia memory write pwait# timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 figure 3-14. pcmcia i/o read timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 figure 3-15. pcmcia i/o read pwait# timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68 figure 3-16. pcmcia i/o write timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 figure 3-17. pcmcia i/o write pwait# timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 figure 3-18. lcd controller timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 figure 3-19. lcd read lwait# timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 figure 3-20. lcd write lwait# timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 figure 3-21. 16-bit chip select little-endian data format (default) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 figure 3-22. big-endian au1 core and little-endian 16-bit chip select . . . . . . . . . . . . . . . . . . . . . . . . . . 72 figure 3-23. big-endian au1 core and big-endian 16-bit chip select . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 figure 5-1. interrupt controller logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 figure 6-1. endpoint configuration data structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 figure 6-2. transmit ring buffer entry format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 figure 6-3. receive ring buffer entry format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 figure 6-4. typical write transaction timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 figure 6-5. typical read transaction timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 figure 7-1. clocking topology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 figure 7-2. frequency generator and clock source block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 figure 7-3. frequency generator and clock source mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 figure 7-4. toy and rtc block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 figure 7-5. gpio logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 figure 7-6. sleep and idle flow diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 figure 7-7. sleep sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 figure 8-1. power-up sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 figure 8-2. hardware reset sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 figure 8-3. runtime reset sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 figure 10-1. au1000? processor external signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217
6 amd alchemy? au1000? processor data book - preliminary list of figures 30360d figure 11-1. voltage undershoot tolerances for input and i/o pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235 figure 11-2. voltage overshoot tolerances for input and i/o pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235 figure 11-3. sdram timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239 figure 11-4. static ram, i/o device and flash timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240 figure 11-5. pcmcia host adapter timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241 figure 11-6. lcd interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242 figure 11-7. gpio interrupt timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243 figure 11-8. ethernet mii timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244 figure 11-9. i2s timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245 figure 11-10. ac-link timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246 figure 11-11. ssi timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247 figure 11-12. ejtag timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248 figure 11-13. power-up sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249 figure 11-14. hardware reset sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250 figure 11-15. runtime reset sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251 figure 12-1. package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257 figure 12-2. connection diagram ? top view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259
amd alchemy? au1000? processor data book - preliminary 7 list of tables 30360d list of tables table 2-1. cache line allocation behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 table 2-2. cache operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 table 2-3. cache coherency attributes (cca) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 table 2-4. values for page size and pagemask register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 table 2-5. cause[exccode] encodings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 table 2-6. cpu interrupt sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 table 2-7. coprocessor 0 register definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 table 3-1. memory controller block base address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 table 3-2. sdram configuration registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 table 3-3. sdram signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 table 3-4. static bus controller configuration registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 table 3-5. device type encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 table 3-6. burst size mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 table 3-7. actual number of clocks for timing parameters (except tcsh) . . . . . . . . . . . . . . . . . . . . . . 56 table 3-8. actual number of clocks for tcsh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 table 3-9. static ram, i/o device and flash control signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 table 3-10. pcmcia memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 table 3-11. pcmcia interface signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 table 3-12. lcd controller interface signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 table 4-1. dma channel base addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 table 4-2. dma channel configuration registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74 table 4-3. peripheral addresses and selectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 table 5-1. interrupt controller connections to the cpu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 table 5-2. interrupt sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 table 5-3. interrupt controller base addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 table 5-4. interrupt controller registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 table 5-5. interrupt configuration register function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 table 6-1. ac97 base address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 table 6-2. ac97 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 table 6-3. ac-link signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 table 6-4. usb host base address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 table 6-5. usb host signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 table 6-6. usb device base address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 table 6-7. usb device register block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 table 6-8. endpoint configuration field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99 table 6-9. example endpoint configuration data block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 table 6-10. usb device signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 table 6-11. irda modes supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 table 6-12. irda base address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 table 6-13. irda registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 table 6-14. irda hardware connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 table 6-15. irda phy configuration table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 table 6-16. fast infrared mode (fir) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 table 6-17. medium infrared mode (mir) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 table 6-18. slow infrared mode (sir) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
8 amd alchemy? au1000? processor data book - preliminary list of tables 30360d table 6-19. transmit ring buffer entry format description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 table 6-20. receive ring buffer entry format description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 table 6-21. ethernet base addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 table 6-22. mac configuration register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 24 table 6-23. mac dma entries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 table 6-24. mac dma receive entry registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 table 6-25. mac dma transmit entry registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 table 6-26. mac dma block indexed address bit definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 table 6-27. ethernet signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 table 6-28. i 2 s base address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 table 6-29. i2s interface register block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 table 6-30. i2s signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 table 6-31. uart register base addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 table 6-32. uart registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 table 6-33. interrupt cause encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 table 6-34. uart signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 table 6-35. ssi base addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 table 6-36. ssi registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 table 6-37. ssi signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 table 7-1. system control block base address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 table 7-2. clock generation registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 table 7-3. clock mux input select values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 table 7-4. programmable counter registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 table 7-5. gpio control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 table 7-6. peripheral power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 table 7-7. power management registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 table 8-1. romsel and romsize boot device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198 table 9-1. coprocessor 0 registers for ejtag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 table 9-2. ejtag memory mapped registers at 0x_ff30_0000 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204 table 9-3. ejtag instruction register values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209 table 9-4. ejtag signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 table 10-2. signal state abbreviations for table 10-3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218 table 10-1. signal type abbreviations for table 10-3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218 table 10-3. signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219 table 11-1. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234 table 11-2. thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235 table 11-3. dc parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236 table 11-4. voltage and power parameters for 266 mhz part . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236 table 11-5. voltage and power parameters for 400 mhz part . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237 table 11-6. voltage and power parameters for 500 mhz part . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237 table 11-7. sdram controller interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239 table 11-8. static ram, i/o device and flash timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240 table 11-9. pcmcia timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241 table 11-10. lcd timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242 table 11-11. gpio timing for interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243 table 11-12. ethernet mii timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244 table 11-13. i2s interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245 table 11-14. ac-link interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246 table 11-15. synchronous serial interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247 table 11-16. ejtag interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248 table 11-17. power-up timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249 table 11-18. hardware reset timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250 table 11-19. runtime reset timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251 table 11-20. external clock extclk[1:0] specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252 table 11-21. 12 mhz crystal specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253
amd alchemy? au1000? processor data book - preliminary 9 list of tables 30360d table 11-22. 32.768 khz crystal specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253 table 12-1. pin assignment ? sorted by pin number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261 table 12-2. pin assignment ? sorted alphabetically by default signal . . . . . . . . . . . . . . . . . . . . . . . . 265 table 12-3. pin assignment ? alternate signals sorted alphabetically . . . . . . . . . . . . . . . . . . . . . . . . 268 table a-1. basic au1000? processor physical memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271 table a-2. system bus devices physical memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271 table a-3. peripheral bus devices physical memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272 table a-4. device memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273 table a-5. revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279 table a-6. edits to current revision . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279
10 amd alchemy? au1000? processor data book - preliminary list of tables 30360d
amd alchemy? au1000? processor data book - preliminary 11 1 overview 30360d 1.0 overview the au1000? processor is a high performance, low power system-on-a-chip (soc) designed for use in the internet edge device market. these devices are customer premise equipment (cpe) products, including both wireless, hand- held enterprise pdas and remote internet access prod- ucts, as well as internet infrastructure products such as routers and line cards. 1.1 product description the au1000? processor is a complete soc based on the mips32? instruction set. desi gned for maximum perfor- mance at low power, the processor runs up to 500 mhz. power dissipation is less than a half watt for the 400 mhz version. highly integrated with on-chip memory controllers and internet access peripherals, the au1000 processor runs a variety of operatin g systems, including windows? ce, linux and vxworks. moreover, the integration of peripherals with the unique, high performance, mips-com- patible core provides low system cost, small form factor, low system power requirement, simple designs at multiple performance points and thus, short design cycles. figure 1-1. au1000? processor block diagram dma controller enhanced mips - 32 cpu core sdram controller 32 x 16 mac bus unit 16kb data cache sram controller system bus peripheral bus fast irda ejtag ethernet mac ethernet mac usb 1.1 host usb 1.1 device interrupt control gpio (32) i 2 s uart (4) sdram lcd controller pcmcia flash sram rom expansion bus rtc (2) power mgmt ssi ssi ac97 controller 16kb inst. cache
12 amd alchemy? au1000? processor data book - preliminary overview 30360d 1.2 features high speed mips cpu core 266, 400, or 500 mhz mips32 instruction set 32-bit architecture 16 kb instruction and 16 kb data caches high speed multiply-accumulate (mac) and divide unit 1.5v core @ 266 mhz and 400 mhz 1.8v core @ 500 mhz 3.3v i/o highly-integrated s ystem peripherals gpio (32 total, 5 dedicated for system use) two 10/100 ethernet mac controllers usb 1.1 device and host controllers four uarts irda controller ac97 controller i 2 s controller two ssi controllers pcmcia interface high-bandwidth memory buses 100 mhz sdram controller (@ 400 mhz) sram/flash eprom controller caches 16 kb non-blocking data cache 16 kb instruction cache instruction and data caches are 4-way set associative write-back with read-allocate cache management features: ? programmable allocation policy ? line locking prefetch instructions (instruction and data) high speed access to on-chip buses core microarchitecture highlights pipeline ? scalar 5-stage pipeline ? load/store adder in i-stage (instr decode) ? scalar branch techniques optimized: pipelined register file access in fetch stage ? zero penalty branch multiply-accumulate (mac) and divide unit ? max issue rate of one 32x16 mac per clock ? max issue rate of one 32x32 mac per every other clock ? operates in parallel to cpu pipeline ? executes all integer multiply and divide instructions ? 32 x 16-bit mac hardware mmu instruction and data watch registers for software break- points separate interrupt exception vector tlb features: ? 32 dual-entry fully-associative ? variable page sizes: 4 kb to 16 mb ?4-entry itb low system power core / power ? 266 mhz / < 300 mw 400 mhz / 500 mw 500 mhz / 900 mw power-saving modes: ?idle ?sleep pseudo-static design to 0 hz package 324 bga, 23 mm x 23 mm operating system support microsoft? windows? ce linux vxworks development tool support complete mips32? compatible tool set numerous 3rd-party compilers, assemblers and debuggers
amd alchemy? au1000? processor data book - preliminary 13 2 cpu 30360d 2.0 cpu the au1000 cpu core is a unique implementation of the mips 32 instruction set architecture (isa) designed for high fre- quency and low power. this chapter provides information on the implementation details of this mips32 compliant core. the full description of the mips32 architecture is provided in the ?mips32 tm architecture for programmers? documenta- tion, available from mips technologies, inc. the informati on contained in this chapter supplements the mi ps32 architec- ture documentation. 2.1 core the au1000 cpu core (au1) is a high performance, low powe r implementation of the mips 32 architecture. figure 2-1 shows a block diagram of the core. the au1 core contains a five-stage pipeline. all stages comple te in a single cycle when data is present. all pipeline hazards and dependencies are enforced by hardware interlocks so that any sequence of instructions is guaranteed to execute cor- rectly. therefore, it is not necessary to pad legacy mips haz ards (such as load delay slots and coprocessor accesses) with nops. the general purpose register file has two read ports and one wr ite port. the write port is shared with data cache loads and the pipeline writeback stage. figure 2-1. au1 core diagram register file mini-itlb instruction cache fetch decode execute cache writeback cp0 registers tlb data cache write buffer system bus interface mac miss hit ejtag system bus
14 amd alchemy? au1000? processor data book - preliminary cpu 30360d 2.1.1 fetch stage the fetch stage retrieves the next instruct ion from the instruction cache, where it is passed to the decode stage. if the instruction is not present in th e instruction cache, then the fetch address is forwarded to the virtual memory unit in order to fulfill the request. instructio n fetch stalls until the next instruction is available. 2.1.2 decode stage the decode stage prepares the pipeline for executing the instruction. in the decode stage, the following occur in parallel: the instruction is decoded. control for the instruction is generated. register data is read. the branch target address is generated. the load/store address is generated. instructions stall in the decode stage if dependent data or resources are not yet av ailable. at the end of the decode stage a new program counter value is sent to the fetch stage for the next instruction fetch cycle. 2.1.3 execute stage in the execute stage, instructions that do not access memory are processed in hardware (shifters, adders, logical, compar- ators, etc.). most instructions comp lete in a single cycle, but a few requ ire multiple cycles (clo, clz, mul). the virtual address calculation begins in the decode stage so th at physical address calculation can complete in the exe- cute stage, in time to initiate the acce ss to the data cache in the execute stage. if the physical address misses in the tlb, a tlb exception is posted. multiplies and divides are forwarded to the multiply accumulate unit. these instructions require multiple cycles to execute and operate mostly independent of the main five-stage pipeline. all exception conditions (arithmetic, tlb, interrupt, etc.) are posted by the end of the execute stage so that exceptions can be signalled in the cache stage. 2.1.4 cache stage in the cache stage, load and store accesses complete. loads that hit in the data cache obtain the data in the cache st age. if a load misses in the data cache, or is to a non-cache- able location, then the request is sent to the system bus to be fulfilled. load data is forwar ded to dependent instructions in the pipeline. stores that hit in the data cache are written into the cache ar ray. if a store misses in the data cache, or is to a non-cache- able location, then the store is sent to the write buffer. if any exceptions are posted, an excepti on is signaled and the au1 core is directed to fetch instructions at the appropriate exception vector address. 2.1.5 writeback stage in the writeback stage, results are posted to the general pur pose register file, and forwarded to other stages as needed. 2.1.6 multiply accumulate unit the multiply accumulate unit (mac) executes all multiply and divide instructions. the mac is composed of a 32x16 bit pipelined array multiplier that supports early out detection, divide block, and the hi and lo registers used in calculations. the mac operates in parallel with the main five-stage pipeline. instructions in the main pi peline that do not have dependen- cies on the mac calculations execute simult aneously with instructions in the mac unit. a multiply calculation of 16x16 or 32x16 bits can complete in one cycle. the 32x16 bit multiply must have the sign- extended 16-bit value in register operand rt of the instruction. 32x32 bit multiplies may be started every other cpu cycle. the 32x32 multiplies will complete in two cycles if the results are written to the general purpose registers.
amd alchemy? au1000? processor data book - preliminary 15 cpu 30360d if the results are written to the hi/lo registers then three c ycles are required for 16x16 and 32x16 bits multiplies. 32x32 bit multiplies that use hi/lo will complete in 4 cycles. divide instructions complete in a maximum of 35 cycles. 2.2 caches the au1 core contains independent, on-chip 16 kb instruction and data caches. as shown in figure 2-2, each cache con- tains 128 sets and is four-way set associative with 32 bytes per way (cache line). figure 2-2. cache organization a cache line is tagged with a 20-bit physical address, a lock bit, and a valid bit. data cache lines also include coherency and dirty status bits. the physical address tag contains bits 31:12 of the physical address; as such, physical addresses in which bits 35:32 are non-zero must be mapped non-cacheable. a cache line address is always 32-byte aligned. the cache is i ndexed with the lower, untranslated bits (bits 11:5) of the vir- tual address, allowing the virtual-to-physical address translation and the cache access to occur in parallel. 2.2.1 cache line replacement policy in general, the caches implement a least recently used (lru ) replacement policy. each cache set maintains true lru sta- tus bits (mru, nmru and lru) to determine which cache line is selected for replacement. however, software can influ- ence which cache line is replaced by marking memory pages as streaming , or by locking lines in the cache. 2.2.2 cache line locking support the cache instruction is used to lock individual lines in the cache. a locked line is not subject to replacement. all four lines in a set can not be locked at once; at leas t one line is always available for replacement. to unlock individual cache lines use the cache instruction with a ?hit invalidate? command opc ode. see section 2.2.5 "cache management" on page 17 for further discussion of the cache instruction. 2.2.3 cache streaming support streaming is typically characterized as the processing of a larg e amount of transient instructions and/or data. in traditional cache implementations (without explicit support for streaming), transient instructions and/or data quickly displace useful, recently used items in the cache. this yields poor utiliza tion of the cache and results in poor system performance. the au1 caches explicitly support stream ing by placing instructions and/or data marked as streaming into way 0 of the cache. this method ensures that streamin g does not purge the cache( s) of useful, recently used items, while permitting transient instructions and/or data to be cached. the cca bits in the tlb entry indi cate if a page contai ns streaming instruc- tions and/or data. in addition, the pref instruction is available to software to allow data to be placed in the data cache in advance of its use. cache line state bit31302928272625242322212019181716151413121110 9 8 7 6 5 4 3 2 1 0 physical address tag d s l v cache address decode bit31302928272625242322212019181716151413121110 9 8 7 6 5 4 3 2 1 0 virtual/physical address set select byte select way 3 word 0 word 1 word 2 word 3 word 4 word 5 word 6 word 7 address tag & state address tag & state address tag & state address tag & state word 0 word 1 word 2 word 3 word 4 word 5 word 6 word 7 word 0 word 1 word 2 word 3 word 4 word 5 word 6 word 7 word 0 word 1 word 2 word 3 word 4 word 5 word 6 word 7 way 2 way 1 way 0 128 sets
16 amd alchemy? au1000? processor data book - preliminary cpu 30360d 2.2.4 cache line allocation behavior when an instruction fetch misses in the instruction cache, or a data load misses in the data cache, a burst fill operation is performed to fill the cache line from memory. the cache line is selected by the following algorithm: mru is most recently used nmru is next most recently used nlru is next least recently used lru is least recently used cache miss: if (streaming cca=6) then replacement = 0, else if (lru is !valid or !locked) then replacement = lru else if (nlru is !valid or !locked) then replacement = nlru else if (nmru is !valid or !locked) then replacement = nmru else replacement = mru cache hit: new mru = hit way in short, the lru selection is true lru but with the following priorities: 1) streaming: cache misses are forced to way 0. 2) locking: cache misses follow policy above and set lock bit. 3) normal: true lru replacement. table 2-1 summarizes cache line allocation for misses, as well as cache hit behavior. the table also shows how prefetch- ing and cache locking affect the cache for hits and misses. table 2-1. cache line allocation behavior operation hit miss normal data load, instruction fetch read data from whichever cache line contains the address. allocate and fill cache line; clear lock bit; return read data. data store write data to whichever cache line contains the address. send to the write buffer. streaming (cca = 6) data load, instruction fetch read data from whichever cache line contains the address. allocate and fill cache line in way 0; maintain lock bit; return read data. data store write data to whichever cache line contains the address. send to the write buffer. pref (data prefetch instruction with 0x4 hint) no action taken? data remains in current cache line. allocate and fill cache line in way 0; maintain lock bit. locking cache 0x1d/0x1c (cache manage- ment instruction with lock opcode) set lock bit in whichever cache line contains the address. allocate and fill cache line; set lock bit.
amd alchemy? au1000? processor data book - preliminary 17 cpu 30360d 2.2.5 cache management the caches are managed with the cache instruction. the effect of the cache instruction is immediately visible to subse- quent data accesses. table 2-2 shows the cache operations, in cluding the opcode to direct the operation to either the instruction cache or data cache. (an ?n/a? indicates that the operation is not applicable.) these cache operations permit initialization, lo cking/unlocking and management of the caches. 2.2.6 cache coherency attributes (cca) the cache coherency attributes (cca) field in config0[k0] an d in the tlb determine the cache-ability of accesses to mem- ory. cached accesses are performed critical-word-first to improve performance. the au1 implements the following: table 2-2. cache operations operation cache[20..18] encoding opcode for instruction cache opcode for data cache index invalidate 000 0x00 0x01 (with writeback) index load tag 001 0x04 0x05 index store tag 010 0x08 0x09 hit invalidate 100 0x10 0x11 fill 101 0x14 n/a hit writeback and invalidate 101 n/a 0x15 hit writeback 110 n/a 0x19 fetch and lock 111 0x1c 0x1d table 2-3. cache coherency attributes (cca) cca cca (3 bits) description 0, 1 00x reserved (undefined). 2 010 uncached, non-mergeable, non-gatherable. required by the mips32 architecture. in addition, data is not merged within the write buffer to achieve a truly uncached effect. 3 011 cached, mergeable, gatherable. 4 100 reserved (undefined). 5 101 cached, mergeable, gatherable. 6 110 cached, mergeable, gatherable, streaming. instructions and/or data are placed into way 0. 7 111 uncached, mergeable, gatherable. even though data is not cached, data stores sent to the write buffer are subject to merging and gathering in the write buffer.
18 amd alchemy? au1000? processor data book - preliminary cpu 30360d 2.2.7 instruction cache the instruction cache is a 16 kb, four-way set associative ca che. the instruction cache serv ices instruction fetch requests from the fetch stage of the pipeline. an instruction cache line state consis ts of a 20-bit physical address tag, a lock bit (l) and a valid bit (v). 2.2.7.1 instruction cache init ialization and invalidation out of reset, all instruction cache lines are invalid ated; thus the instruction cache is ready for use. to invalidate the instruction cache in software, a loop of index invalidate cache instructions for each of the lines in the cache invalidates the cache. li t0,(16*1024) # cache size li t1,32 # line size li t2,0x80000000 # first kseg0 address addu t3,t0,t2 # terminate address of loop loop: cache 0,0(t2) # icache indexed invalidate tag addu t2,t1 # compute next address bne t2,t3,loop nop 2.2.7.2 instruction cache line fills if an instruction fetch address hits in the instruction cache, the instru ction word is returned to the fetch stage. if the fetc h address misses in the cache, and the address is cacheable, then the instruction cache performs a burst transfer from the memory subsystem to fill a cache line, and retu rns the instruction word to the fetch stage. the instruction cache line is selected by the replacement policy described in section 2.2.1 "cache line replacement pol- icy" on page 15. 2.2.7.3 instruction cache coherency the instruction cache does not maintain coherency with the data cache. coherency between the instruction cache and the data cache is the responsibility of software. however, th e data cache snoops during instruction cache line fills. maintaining coherency is important when loading programs into memory, creating exception vector tables, or for self-modi- fying code. in these circumstances, memory is updated with new instructions using store instructions which places the new instructions in the data cache, but not in the instruction cache (thus the instruction cac he may contain old instructions). to maintain coherency, software must use the cache instruction to invalidate the modified range of program addresses in the instruction cache. because th e data cache snoops during instruction cache line fills, it is not necessary to writeback the data cache prior to invalidating the instruction cache. an in struction fetch to the newly l oaded/modified program correctly fetches the new instructions. 2.2.7.4 instruction cache control the cache-ability of instructions is controlled by three mechanisms: config0[k0] field the cca bits in the tlb the cache instruction the config0[k0] field contains a cache coherency attribute (cca) setting to control the cache-ability of kseg0 region. at reset, this field defaults to cca=3 (cacheable). the cca bits in the tlb entry control the cache-ability of the kuseg, kseg2, and kseg3 regions. each tlb entry spec- ifies a cca setting for the pages mapped by the tlb. instruction cache line state bit31302928272625242322212019181716151413121110 9 8 7 6 5 4 3 2 1 0 physical address tag lv
amd alchemy? au1000? processor data book - preliminary 19 cpu 30360d the cache instruction manages the caches, including the ability to lo ck lines in the cache. valid instruction cache opera- tions are the following: index invalidate index load tag index store tag hit invalidate fill fetch and lock the effect of the cache instruction is visible to subsequent instructions not already in the pipeline. instructions already in the fetch and decode stages of the pipeline are not affect ed by a cache operation on the instruction cache. 2.2.8 data cache the data cache is a 16kb four-way set associative write-bac k cache. data cache accesses are distributed across the exe- cute and cache pipeline stages. a data cache line state consists the 20-bit physical address tag, a dirty bit (d), a coherency bit (s), a lock bit (l) and a va lid bit (v). the data cache employs a read-allocate policy. cache lines can be replaced on loads, but no t on stores. stores that miss in the data cache are forwarded to the write buffer. the data cache supports hit-under-miss for one outstanding miss. if an access misses in the data cache, the data cache services the next access whil e the memory subsystem provides the data for the missed access. if the next access hits in the data cache, the data is available immediately; otherwise t he cache stalls the access unti l the first access completes. 2.2.8.1 data cache initia lization and invalidation out of reset, all data cache lines are inva lidated; thus the data ca che is ready for use. to invalidate the data cache in software, a loop of indexed writeback invalidate cache instructions for each of the lines in the cache invalidates the cache. li t0,(16*1024) # cache size li t1,32 # line size li t2,0x80000000 # first kseg0 address addu t3,t0,t2 # terminate address of loop loop: cache 1,0(t2) # dcache indexed invalidate tag addu t2,t1 # compute next address bne t2,t3,loop nop 2.2.8.2 data cach e line fills a data cache access is initiated in the execute stage which allo ws a cache hit or miss indication and all exceptions to be signaled early in the cache stage. if the data address hits in the data cache, the data is available in the cache stage. if the data address misses in the data cache, and the address is cach eable, the data cache performs a burst fill to a cache line, forwarding the critical word to the cache stage. the data cache line is selected by the replacement policy de scribed in section 2.2.1 "cache line replacement policy" on page 15. if the line selected contains modified data (cache line is valid and has its dirty bit set by a store hit), then the c ache line is moved to a cast-out buffer, the cache line is filled from memory and the load request fulfilled, and then the cast-out buffer is written to memory. data cache line state bit31302928272625242322212019181716151413121110 9 8 7 6 5 4 3 2 1 0 physical address tag dslv
20 amd alchemy? au1000? processor data book - preliminary cpu 30360d 2.2.8.3 data cache coherency the data cache snoops coheren t system bus transactions to maintain data c oherency with other system bus masters (i.e. dma). if a coherent read transaction on the system bus hits in the data cache, the data cache provides the data. if a coher- ent write transaction on the system bus hits in the data cache, the data cache updates its inte rnal array with the data. if a coherent transaction (read or write) misses in the data ca che, the data cache array is unchanged by the transaction. loads and stores which hit in the data cache can bypass prev ious stores in cacheable regions. the read-allocate data cache policy forwards store-misses to the write buffer. subsequent loads and stores which hit in the data cache, and to a different cache line address than store-misses, are fulfilled imme diately (while store-misses may still be in the write buffer) . however, if a load address hits in a cache-line address of an item in the write buffer, the lo ad is stalled until the write buf fer commits the corresponding store. the data cache also maintains coherency with other caching masters. when a load is serviced from another caching mas- ter, both caching masters set the shared bi t for the affected cache line. then if a store occurs to a data cache line with the shared bit set, the cache line address is broadcast on the system bus to invalidate cache lines in other caching masters that contain the same address. the data cache is single-ported; therefor e transactions on the system bus are prio ritized over accesses by the core. how- ever, the data cache design prevents the system bus from saturating the data cach e indefinitely, which ensures that the core can make forward progress. when changing the cca encoding in config0[k0] or the tlb to a different cca encoding, so ftware must ensure that data integrity is not compromised by first pushi ng modified (dirty) data to memory within the page. this is especially important when changing from a coherent cca encoding to a non-coherent cca encoding. 2.2.8.4 data cache control the cache-ability of data accesses is controlled by four mechanisms: config0[k0] field the cca bits in the tlb the cache instruction the pref instruction the config0[k0] field contains a cache coherency attribute (cca) setting to control the cache-ability of kseg0 region. at reset, this field defaults to 011b, cacheable. the cca bits in the tlb entry control the cache-ability of the kuseg, kseg2, and kseg3 regions. each tlb entry spec- ifies a cca setting for the pages mapped by the tlb. the cache instruction manages the caches; including the ability to lock lines in the cache. valid data cache operations are: index writeback invalidate index load tag index store tag hit invalidate (unlocks) hit writeback and invalidate hit writeback fetch and lock the effect of the cache instruction is immediately visible to subsequent data accesses. the pref instruction places data into the data cache. the following prefetch hints are implemented: 0x00 - normal load 0x04 - streaming load the streaming load hint directs the data be placed into way 0 of the data cache (eve n if the line is locked), thus permitting transient data to be cached and non-transient data to remain in the cache for improved performance. data cache streaming support combined with the pref instruction enhances multimedia processing.
amd alchemy? au1000? processor data book - preliminary 21 cpu 30360d 2.3 write buffer the au1 write buffer is depicted in figure 2-3. all non-cach eable processor stores and data cache store-misses (the data cache is a read-allocate policy) ar e routed through the write buffer. figure 2-3. au1 write buffer the write buffer is a 16-word deep first-in-f irst-out (fifo) queue. all pr ocessor stores arrive first at the merge latch, where merging and gathering decisions are performed, and then travel through the queue. the write buffer arbitrates for the sys- tem bus to perform consolidated transfers to the main memory. a write buffer fifo entry c ontains the address (word address), the data and associated byte masks (bm), and two control bits. the four bm bits indicate which by tes within the word contain valid data. t he two control bits are the valid bit which indicates if the entry is valid, and the closed (c) bit. when a c bit is set, the write buffer initiates a request to the syste m bus so that it can transfer data to memory. the circ umstances for which the c bit is set are described below. the write buffer is capable of variable-length burst writes to memory. the length can vary from one word to eight words, and is determined by the c bits in the write buffer. during each beat of the burst, the appropr iate bytes to write are selected from the corresponding byte masks. as each entry is written to memory, it is popped from the fifo, advancing each entry in the fifo by one. in other words, entry 0 is always presented to t he system bus for writing. when the write buffer has at least one empty entry, processor stores do not stall, thus improving processor performance. the write buffer is disabled by setting config0[wd] to 1. in this instance, all non-cacheable and data cache store-misses stall until the write completes. the remaining description of the write buffer operation assumes config0[wd] is 0. out of reset, config0[wd] is 0. 0 15 system bus data address merge latch cv35 0 bm31 0
22 amd alchemy? au1000? processor data book - preliminary cpu 30360d 2.3.1 merge latch all processor stores first arrive at the merge latch. logic with in the merge latch decides what action to take with the incom- ing data. 1) the incoming address is the same word address as the merge latch address. this case is for merging, which occurs within the merge latch itself. 2) the incoming word address is sequentially adjacent to the merge latch word address (incoming address is merge latch address + 4). this case is for gathering. the merge latch contents are propagated to the fi fo with the c bit cleared for this entry. 3) neither 1 nor 2 is true. the merge latch contents are propagated to the fifo with the c bit set for this entry. if the merge latch contents ar e propagated to the fifo, the incoming address and data are placed in the merge latch for future comparisons. furthermore, if the incoming address is t he last word address of the maximum burst line size (the least significant 5 bits are 0x1c), then the c bit is set. 2.3.2 write buffer merging write buffer merging combines stores destined for the same word address . merging places the incoming data into the appropriate data byte(s) within the merge latch. write buffer merging is particularly useful for sequential, incremental address write operations, such as string operations. with write buffer merging, the writes are merged into 32-bit writes which reduces the number of accesses to the memory and increases the effective throughput to main memory. this example demonstrates merging: thes e five byte writes occur in sequence: 0x_0000_1000 = 0xab 0x_0000_1001 = 0xcd 0x_0000_1002 = 0xde 0x_0000_1003 = 0xef 0x_0000_1002 = 0xbe after the first four writes, the data in the merge latch contains 0xabcddeef. however, after the fifth write, the merge latch data now contains 0xabcdbeef. so long as the incoming word address is the same as the me rge latch word address, the data can change without a proces- sor stall or access to memory. write buffer merging is controlled by the config[nm] bit and the tlb[cca] setting. when config0[nm] is 1 or tlb[cca] is 2, the merge latch does not perform merging. conversely, conf ig0[nm] is 0 or tlb[cca] is not 2 enables merging. out of reset, config0[nm] is 0. note: merging takes place only in the merge latch. as such, writ es to an address which are in the fifo (but not in the merge latch) do not merge. in the example below, writes to 0x_0000_1000 and 0x_0000_1002 do not merge because the intervening write to address 0x_0000_1005 is not in the same word address which caused 0x_0000_1000 to leave the merge latch. 0x_0000_1000 = 0xab 0x_0000_1005 = 0xcd 0x_0000_1002 = 0xde
amd alchemy? au1000? processor data book - preliminary 23 cpu 30360d 2.3.3 write buffer gathering write buffer gathering combines sequentially adjacent word addresses for burst transfers to the main memory. when a c bit is set, all queue entries from zero (0) up to and including th e entry with its c bit set (n) are written to main memory in a single burst. write buffer gathering is particularly useful for sequential, incremental address store operations, such as string operations. with write buffer gathering, the stores are combined into burs ts up to 32-bytes (eight words) in length which reduces the number of accesses to the memory and increases effective throughput. here is an example of an eight-word burst. the burst coul d result from code which seque ntially writes words (optimized memcpy(), for example). these eight word writes occur in sequence: 0x00001000 0x00001004 0x00001008 0x0000100c 0x00001010 0x00001014 0x00001018 0x0000101c the entries corresponding to word addresses 0x00001000 through 0x00001018 have c bit set to zero. when address 0x0000101c arrives, its c bit is set. when the write buffer is granted t he system bus, it bursts all eight entries to main mem- ory. here is an example of two-word burst. this burst may be typi cal of application software. thes e four word writes occur in sequence: 0x00001000 0x00001004 0x0000100c 0x00001008 the c bit is cleared for the 0x00001000 entry and is set for the 0x00001004 entry. these two words are then burst to main memory. the 0x0000100c entry also has its c bit set, and is written to memory. the 0x00001008 will reside in the merge latch until displaced by a subsequent store. 2.3.4 write buffer reads when a read from memory is initiated, the read cache-line address (a35..a5) is compared against all cache-line addresses in the write buffer. if the read cache-line address matches a writ e buffer cache-line address, t he read is stalled. the write buffer then flushes entries to memory until the read address no longer matches a write buffer cache-line address. the read is then allowed to complete. the write buffer ensures data integrity by not allowing reads to bypass writes. 2.3.5 write buffer coherency non-cacheable stores and/or data cache stor e-misses reside in the write buffer, possibly indefinitely. furthermore, the write buffer does not snoop system bus transactions (e.g. integrat ed peripheral dma engines). to ensure the write buffer con- tents are committed to memory, a sync instruction must be issued. issuing a sync instruction prior to enabling each dma transfer from memory buffers and/or structures is necessary. with- out the sync , the dma engine may retrieve incomplete buffers and/or structures (the remainder of which may be in the write buffer). issuing a sync instruction after a store to an i/o region where st ores have side effects is necessary. without the sync instruction, the store may not leave the write buffer to achi eve the side effects (e.g. clearing an interrupt acknowledge bit). note that a read access does not guarantee a complete write bu ffer flush since the write buffer flushes as few entries as necessary until the read address no longer matches an address in the write buffer.
24 amd alchemy? au1000? processor data book - preliminary cpu 30360d 2.4 virtual memory the au1 implements a tlb-based virtual address translation un it which is compliant with th e mips32 specification. this scheme is similar to the r4000 tlb and cp0 implementation. the ?mips32 architecture for programmers volume iii? con- tains all the information relevant to a tlb-based virtual address translation unit. the virtual address translation architecture is composed of a ma in 32-entry fully associative tlb array. to improve instruc- tion fetch performance, a 4-entry fully a ssociative instruction tlb is implemented. this miniature instruction tlb is fully coherent with the main tlb array and is completely transparent to software. each tlb entry maps a 32-bit virtual address to a pair of 36-bit physical addresses. the page size of a tlb entry is vari- able under software control, from 4 kb to 16 mb. a tlb entry is described below. the size of the page(s) that the tlb entry translates is determined by pa gemask. the valid values for pagemask range from 4 kb to 16 mb, according to table 2-4. the pagemask determines the number of significant bits in the 32-bit address generated by the program (either as a load/ store address or an instruction fetch address). the upper, signifi cant bits of the program address are compared against the upper, significant bits of vpn2. when an address match o ccurs, the even/odd pfn select bit of the program address selects either pfn0 (even) or pfn1 (odd) as the upper bits of the resulting 36-bit physical address. the tlb mechanism permits mapping a larger, 36-bit physical address space into the smaller 32-bit program address space. the au1 implements an internal 36-bit physical addre ss system bus (sbus) which is then decoded by integrated peripherals, and by chip-selects for external memories and peripherals. the cache coherency attributes (cca) of the physical page are controlled by the tlb entry. the valid values are described in table 2-3. in general, i/o spaces require a non-cacheabl e setting, whereas memory can utilize a cacheable setting. note: physical addresses in which address bits 35:32 ar e non-zero must be mapped non-cached (cca = 2). the tlb array is managed completely by software. software c an implement a tlb replacement al gorithm that is either ran- dom (via the tlbwr instruction) or deterministic (via the tlbwi instruction). hardware is available to segment the tlb via the wired register so different replacement strategies can be us ed for different areas of the tlb. tlb entry bit313029282726252423222120191817161514131211109876543210 pagemask 0 pagemask 0 entryhi vpn2 0 asid entrylo0 0 0 pfn0 c0 d0 v0 g entrylo1 0 0 pfn1 c1 d1 v1 g table 2-4. values for page size and pagemask register page size pagemask register bits 28:13 pfn select bit 4 kb 0x00000000 0000000000000000 12 16 kb 0x00006000 0000000000000011 14 64 kb 0x0001e000 0000000000001111 16 256 kb 0x0007e000 0000000000111111 18 1 mb 0x001fe000 0000000011111111 20 4 mb 0x007fe000 0000001111111111 22 16 mb 0x01ffe000 0000111111111111 24
amd alchemy? au1000? processor data book - preliminary 25 cpu 30360d 2.5 exceptions the au1 core implements a mips32 compliant exception sc heme. the scheme consists of the exception vector entry points in both kseg0 and kseg1, and the exception code (exccode ) encodings to determine the nature of the exception. 2.5.1 exception causes the nature of an exception is reported in the cause[exccode] field. the au1 core can generate the following exceptions: the au1 core does not implement hardware floating-point. as a result, all floating-point instructions generate the reserved instruction (ri) exception, which permits floating-point operations to be emulated in software. in addition, the au1 core does not reco gnize soft reset, non-maskable interrupt (nmi), or cache error exception condi- tions. table 2-5. cause[exccode] encodings exccode mnemonic description 0 int interrupt 1 mod tlb modification exception 2 tlbl tlb exception (load or instruction fetch) 3 tlbs tlb exception (store) 4 adel address error exception (load or instruction fetch) 5 ades address error exception (store) 6 ibe bus error exception (instruction fetch) 7 dbe bus error exception (data reference: load or store) 8 sys syscall exception 9 bp breakpoint exception 10 ri reserved inst ruction exception 11 cpu coprocessor unusable exception 12 ov arithmetic overflow exception 13 tr trap exception 23 watch reference to watchpoint address 24 mcheck machine check (duplicate tlb entry)
26 amd alchemy? au1000? processor data book - preliminary cpu 30360d 2.5.2 interrupt architecture the au1 core implements a mips32 compliant interrupt mechani sm in which eight interrupt sources are presented to the core. each interrupt source is individually maskable to either enable or disable the core from detecting the interrupt. inter- rupts are generated by software, integrated interrupt controllers, performance counters and timers, as noted in table 2-6. all interrupt sources are equal in priority; that is, the interr upt sources are not prioritized in hardware. as a result, softw are determines the relative priority of the interrupt sources. when cause[exccode]=0, software must examine the cause[ip] bits to determine which interrupt source is requesting the interrupt. for more information on interrupt controller 0 and 1 see section 5.0 on page 81. table 2-6. cpu interrupt sources interrupt source cp0 cause register bit cp0 status register bit software interrupt 0 8 8 software interrupt 1 9 9 interrupt controller 0: request 0 request 1 10 11 10 11 interrupt controller 1: request 0 request 1 12 13 12 13 performance counters 14 14 count/compare 15 15
amd alchemy? au1000? processor data book - preliminary 27 cpu 30360d 2.6 mips32? instruction set the au1 core implements the instruction set defined in ?m ips32 architecture for programmers volume ii: the mips32 instruction set?. the floating-point instructions are not impl emented in the au1 core, but may be emulated in software. the mips32 isa is characterized as a co mbination of the r3000 user level inst ructions (mipsii) and the r4000 memory management and kernel mode instructions (32-bit mipsiii). 2.6.1 cache instruction the cache instruction permits management of the au1 instructi on and data caches. the valid operations are listed in table 2-2 "cache operations" on page 17. for data cache operations, the effect of the cache instruction is immediately visibl e to subsequent data accesses. how- ever, for instruction cache operations, the effect of the cache instruction is not visible to subsequent instructions already in the au1 core pipeline. therefore, care should be exer cised if modifying instructio n cache lines containing the cache and subsequent instructions. when issuing the cache instruction with indexed operations (index inva lidate, index load tag and index store tag) the format of the effective address is as follows: the effective address base should be 0x80000000 (kseg0) to avoid possible tlb exceptions, and place zeros in the remainder of the effective address. the format correlates to a 16kb cache that is 4-way set associative with 128 sets and 32-byte line size. software must not use the index store tag cache operation to change the dirty, lock and shared state bits. to set the lock bit, software must use the fetch and lock cache operation. the index load tag and index store tag cache operations utilize cp0 registers dt ag, ddata, itag and idata. the for- mat of data for index tag operations is depicted in the description of these registers. cache operations that require an effective address (i.e. no t the index operations) do not generate the address error exception or trigger data watchpoint exceptions. 2.6.2 pref instruction the pref instruction prefetches data into the data cache. data is prefetched to improve algorithm performance by placing the data in the cache in advance of its use, thus minimizing stalls due to data cache load misses. see also section 2.2.8.4 "data cache control" on page 20 for more on how to use pref . if the effective addr ess computed by the pref instruction does not translate in the tlb (i.e. the address would cause a tlbl exception), no exception is generated and the cache is unchanged. the au1 core implements the following pref instruction hints: 0x00 - normal load 0x04 - streaming load a pref instruction using any other hint value becomes a nop for the au1 core. 2.6.3 wait instruction the wait instruction places the au1 core in one of two low power modes: idle0 and idle1. the low power mode is encoded in the wait instruction bits 24:6 (implement ation-dependent code). a value of 0 selects idle0, and the value 1 selects idle1. other values are not supported and must not be used. in the idle0 low power mode, the au1 core stops clocks to all possible core unit s but continues to sn oop the system bus to maintain data coherency. in the idle1 low power mode, the au1 core stops clocks to all possible core units, including the data cache, so data coher- ency is no longer maintained. cache index operation address decode bit31302928272625242322212019181716151413121110 9 8 7 6 5 4 3 2 1 0 0x8000 way set/index byte select
28 amd alchemy? au1000? processor data book - preliminary cpu 30360d in either idle mode, the general purpose registers and the cp0 registers are preserved, so that when idle mode is exited by an appropriate event, the au1 core resumes processing instructions in exactly the same context as prior to entering idle mode. to enter the low power mode, the wait instruction must be followed by at least four nops, and the entire instruction sequence must be fetched from the instruction cach e. more specifically, if the core fetches the wait and nop instructions from main memory, then the mechanisms for accessing memory will prevent the core from entering low power mode. this is the recommended code sequence: .global au1_wait au1_wait: la t0,au1_wait # obtain address of au1_wait cache 0x14,0(t0) # fill icache with first 8 insns cache 0x14,32(t0) # fill icache with next 8 insns sync nop wait 0 nop nop nop nop j ra when the au1 core is in idle mode, the count register in crements at an unpredictable rate ; therefore the count/compare registers can not be used as the system timer tick when using the wait instruction to enter an idle mode. 2.7 coprocessor 0 coprocessor 0 (cp0) is resp onsible for virtual memory, cache and system control. the mips32 isa provides for differentiation of the cp0 impl ementation. the au1 core has a unique cp0 that is compliant with mips32 specification. the au1 cp0 registers are listed in table 2-7. table 2-7. coprocessor 0 register definitions register number sel register name description compliance (note 1) 0 0 index pointer into tlb array required 1 0 random pseudo-random tlb pointer required 2 0 entrylo0 low half of tlb entry for even pages required 3 0 entrylo1 low half of tlb entry of odd pages required 4 0 context pointer to a page table entry required 5 0 pagemask variable page size select required 6 0 wired number of locked tlb entries required 7 0 reserved reserved 8 0 badvaddr bad virtual address required 9 0 count cpu cycle count required 10 0 entryhi high half of tlb entries required 11 0 compare cpu cycle count interrupt comparator required 12 0 status status required 13 0 cause reason for last exception required 14 0 epc program counter of last exception required 15 0 prid processor id and revision required
amd alchemy? au1000? processor data book - preliminary 29 cpu 30360d 2.7.1 index register (cp0 register 0, select 0) the index register is required for tlb-bas ed virtual address translation units. 16 0 config configuration registers (aka config0) required 16 1 config1 configuration register 1 required 17 0 lladdr load link address optional 18 0 watchlo data memory break point low bits optional 18 1 iwatchlo instruction fetch breakpoint low bits optional 19 0 watchhi data memory break point high bits optional 19 1 iwatchhi instruction fetch breakpoint high bits optional 20 0 reserved reserved 21 0 reserved reserved 22 0 scratch scratch register au1 23 0 debug ejtag control register optional 24 0 depc pc of ejtag debug exception optional 25 0 reserved reserved au1 reserved 25 1 reserved reserved au1 reserved 26 0 reserved reserved 27 0 reserved reserved 28 0 dtag data cache tag value au1 28 1 ddata data cache data value au1 29 0 itag instruction cache tag value au1 29 1 idata instruction cache data value au1 30 0 errorepc program counter at last error required 31 0 desave ejtag debug exception save register optional note 1. a compliance of ?required? denotes a register required by the mips32 architecture. ?o ptional? denotes an optional register in the mips32 architecture which is implemented in the au1 core. ?au1? denotes an optional register unique to the au1 core. ?reserved? denotes a register that is not implemented. index cp0 register 0, select 0 bit31302928272625242322212019181716151413121110 9 8 7 6 5 4 3 2 1 0 p0 index def.x00000000000000000000000000xxxxx bits name description r/w default 31 p probe failure. r unpred 30:5 reserved reserved. must always write zeros, always reads zeros r 0 4:0 index tlb index r/w unpred table 2-7. coprocessor 0 register definitions (continued) register number sel register name description compliance (note 1)
30 amd alchemy? au1000? processor data book - preliminary cpu 30360d 2.7.2 random register (cp0 register 1, select 0) the random register is required for tl b-based virtual address translation units. 2.7.3 entrylo0, entrylo1 register (cp0 registers 2 and 3, select 0) the entrylo0 and entrylo1 registers are required for tlb-based virtual address translation units. 2.7.4 context register (cp0 register 4, select 0) the context register is required for tl b-based virtual address translation units. 2.7.5 pagemask register (cp0 register 5, select 0) the pagemask register is required for tl b-based virtual address translation units. random cp0 register 1, select 0 bit31302928272625242322212019181716151413121110 9 8 7 6 5 4 3 2 1 0 0 random def.00000000000000000000000000011111 bits name description r/w default 31:5 reserved reserved. must always write zeros, always reads zeros r 0 4:0 random tlb random index r 31 entrylo0, entrylo1 cp0 registers 2 and 3, select 0 bit31302928272625242322212019181716151413121110 9 8 7 6 5 4 3 2 1 0 0pfn cdvg def.0 0xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx bits name description r/w default 31:30 reserved reserved. ignored on writes, returns zero on read r 0 29:6 pfn page frame number. corresponds to physical address bits 35..12. r/w unpred 5:3 c cache coherency attribute of the page. see table 2-3 "cache coher- ency attributes (cca)" on page 17. r/w unpred 2 d dirty bit. r/w unpred 1 v valid bit r/w unpred 0 g global bit r/w unpred context cp0 register 4, select 0 bit31302928272625242322212019181716151413121110 9 8 7 6 5 4 3 2 1 0 ptebase badvpn2 0 def.xxxxxxxxxxxxxxxxxxxxxxxxxxxx0 0 0 0 bits name description r/w default 31:23 ptebase used by the operating system as a pointer into the current pta array in memory. r/w unpred 22:4 badvpn2 contains virtual address bits 31..13 upon a tlb exception. r unpred 3:0 reserved reserved. r 0 pagemask cp0 register 5, select 0 bit31302928272625242322212019181716151413121110 9 8 7 6 5 4 3 2 1 0 0mask 0 def.0 0 0xxxxxxxxxxxxxxxx0 0 0 0 0 0 0 0 0 0 0 0 0
amd alchemy? au1000? processor data book - preliminary 31 cpu 30360d 2.7.6 wired register (cp0 register 6, select 0) the wired register is required for tlb-based virtual address translation units. 2.7.7 badvaddr register (cp0 register 8, select 0) the badvaddr register is required for tlb-based virtual address translation units. 2.7.8 count register (cp0 register 9, select 0) the count register is a requir ed register for a constant rate timer. this counter increments 1:1 with the core frequency. during idle0 or idle1 mode, the count register increments at an unpredictable rate; therefore the count/compare regis- ters can not be used as the syst em timer tick when using the wait instruction to enter an idle mode. during sleep mode, this register will not increment. bits name description r/w default 31:29 reserved reserved. ignored on write, returns zero on read. r 0 28:13 mask the mask field is a bit mask in which a ?1? bit indicates that the corre- sponding bit of the virtual address should not participate in the tlb match. see table 2-4 "values for page size and pagemask regis- ter" on page 24. r/w unpred 12:0 reserved reserved. ignored on write, returns zero on read. r 0 wired cp0 register 6, select 0 bit31302928272625242322212019181716151413121110 9 8 7 6 5 4 3 2 1 0 0 wired def.00000000000000000000000000000000 bits name description r/w default 31:5 reserved reserved. ignored on write, returns zero on read. r 0 4:0 wired tlb wired boundary r/w 0 badvaddr cp0 register 8, select 0 bit31302928272625242322212019181716151413121110 9 8 7 6 5 4 3 2 1 0 badvaddr def.xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx bits name description r/w default 31:0 badvaddr bad virtual address r unpred count cp0 register 9, select 0 bit31302928272625242322212019181716151413121110 9 8 7 6 5 4 3 2 1 0 count def.00000000000000000000000000000000 bits name description r/w default 31:0 count interval counter r/w 0
32 amd alchemy? au1000? processor data book - preliminary cpu 30360d 2.7.9 entryhi register (cp0 register 10, select 0) the index register is required for tlb-bas ed virtual address translation units. 2.7.10 compare register (cp0 register 11, select 0) the compare register is a required register for gener ating an interrupt from th e constant rate timer. 2.7.11 status register (cp0 register 12, select 0) the status register is a r equired register for general control of the processor. entryhi cp0 register 10, select 0 bit31302928272625242322212019181716151413121110 9 8 7 6 5 4 3 2 1 0 vpn2 0 asid def.xxxxxxxxxxxxxxxxxxx0 0 0 0 0xxxxxxxx bits name description r/w default 31:13 vpn2 virtual address bits 31..13. r/w unpred 12:8 reserved reserved. ignored on write, returns zero on read. r 0 7:0 asid address space identifier r/w unpred compare cp0 register 11, select 0 bit31302928272625242322212019181716151413121110 9 8 7 6 5 4 3 2 1 0 compare def.xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx bits name description r/w default 31:0 compare interval counter compare value r/w unpred status cp0 register 12, select 0 bit31302928272625242322212019181716151413121110 9 8 7 6 5 4 3 2 1 0 000cu0rp0 re 0 0 bev 0 sr nmi 0 0 0im0 0 0 um 0 erl exl ie def.00000000010000000000000000000100 bits name description r/w default 31 cu3 this bit is zero. coproc essor 3 is not implemented. r 0 30 cu2 this bit is zero. coproc essor 2 is not implemented. r 0 29 cu1 this bit is zero. coproc essor 1 is not implemented. r 0 28 cu0 controls access to coprocessor 0. r/w 0 27 rp reduced power. this bit has no effect. r/w 0 25 re reverse-endian. r/w 0 22 bev boot exception vectors. r/w 1 20 sr soft reset. r/w 0 19 nmi non-maskable interrupt r/w 0 15:8 im interrupt mask r/w 0 4 um user-mode. r/w 0 3 r0 this bit is zero; supervisor-mode not implemented r 0 2erl error level r/w 1 1 exl exception level r/w 0 0 ie interrupt enable r/w 0
amd alchemy? au1000? processor data book - preliminary 33 cpu 30360d 2.7.12 cause register (cp0 register 13, select 0) the cause register is a required regist er for general exception processing. 2.7.13 exception program counter (cp0 register 14, select 0) the exception program counter (epc) register is a required register for general exception processing. 2.7.14 processor identification (cp0 register 15, select 0) the prid register is a required regi ster for processor identification. cause cp0 register 13, select 0 bit31302928272625242322212019181716151413121110 9 8 7 6 5 4 3 2 1 0 bd 0 ce 0 iv wp 0 ip 0 exccode 0 def.00000000000000001000000000000000 bits name description r/w default 31 bd exception in branch delay slot r 0 29:28 ce coprocessor error r 0 23 iv interrupt vector r/w 0 22 wp watchpoint exception deferred r/w 0 15:10 ip[7:2] hardware interrupts pending r 0x20 9:8 ip[1:0] software interrupts pending r/w 0 6:2 exccode exception code r 0 epc cp0 register 14, select 0 bit31302928272625242322212019181716151413121110 9 8 7 6 5 4 3 2 1 0 epc def.xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx bits name description r/w default 31:0 epc exception program counter r/w unpred prid cp0 register 15, select 0 bit31302928272625242322212019181716151413121110 9 8 7 6 5 4 3 2 1 0 company options company id processor id revision def.00000000000000110000001000000000 bits name description r/w default 31:24 company options system-on-a-chip (soc) identification: 0 au1000 1 au1500 2 au1100 r0 23:16 company id company id assigned by mips technologies. amd?s id = 3. r 3 15:8 processor core id identifies the core revision: 0 reserved 1 au1 revision 1 2 au1 revision 2 r2 7:0 revision contains a manufacturing-specific revision level. 0 silicon stepping da; silicon revision 1.1 1 silicon stepping ha; si licon revision 2.1 2 silicon stepping hb; si licon revision 2.2 3 silicon stepping hc; silicon revision 2.3 4 silicon stepping hd; silicon revision 2.4 rsoc specific
34 amd alchemy? au1000? processor data book - preliminary cpu 30360d 2.7.15 configuration register 0 (cp0 register 16, select 0) the config0 register is a required register fo r various processor configuration and capability. 2.7.16 configuration register 1 (cp0 register 16, select 1) the config1 register is a required register fo r various processor configuration and capability. config0 cp0 register 16, select 0 bit31302928272625242322212019181716151413121110 9 8 7 6 5 4 3 2 1 0 mct dd cd um wd nm sm od 0 0 tm be at ar mt 0k0 def.10000000000000001000000010000011 bits name description r/w default 31 m denotes config1 register available at select 1 r 1 30:26 ct reserved. must write 0. r/w 0 25 dd reserved. must write 0. r/w 0 24 cd reserved. must write 0. r/w 0 23 um reserved. must write 0. r/w 0 22 wd reserved. must write 0. r/w 0 21 nm reserved. must write 0. r/w 0 20 sm reserved. must write 0. r/w 0 19 od reserved. must write 0. r/w 0 16 tm reserved. must write 0. r/w 0 15 be indicates the endian mode. r 1 14:13 at architecture type is mips32. r 0 12:10 ar architecture revision is revision 1. r 0 9:7 mt mmu type is standard tlb. r 1 2:0 k0 kseg0 is cacheable, coherent. r/w 3 config1 cp0 register 16, select 1 bit31302928272625242322212019181716151413121110 9 8 7 6 5 4 3 2 1 0 0 mmu size - 1 is il ia ds dl da c2 md pc wr ca ep fp def.00111110011000110011000110001010 bits name description r/w default 30:25 mmu size - 1 number of entries in the tlb minus one. the tlb has 32 entries. r 31 24:22 is instruction cache sets per way is 128. r 1 21:19 il instruction cache line size is 32 bytes. r 4 18:16 ia instruction cache associativity is 4-way. r 3 15:13 ds data cache sets per way is 128. r 1 12:10 dl data cache line size is 32 bytes. r 4 9:7 da data cache associativity is 4-way. r 3 6 c2 coprocessor 2 is not implemented. r 0 5 md always returns zero on read. r 0 4 pc performance counter registers are not implemented. r 0 3 wr watchpoint registers are implemented. r 1 2 ca code compression is not implemented. r 0 1 ep ejtag is implemented. r 1 0 fp fpu is not implemented. r 0
amd alchemy? au1000? processor data book - preliminary 35 cpu 30360d 2.7.17 load linked address register (cp0 register 17, select 0) the lladdr register provides the physical address of the most recent load linked instruction. 2.7.18 data watchlo register (cp0 register 18, select 0) the watchlo and watchhi registers are the interface to the data watchpoint facility. 2.7.19 instruction watchlo register (cp0 register 18, select 1) the iwatchlo and iwatchhi registers are the inte rface to the instruction watchpoint facility. lladdr cp0 register 17, select 0 bit31302928272625242322212019181716151413121110 9 8 7 6 5 4 3 2 1 0 lladdr def.xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx bits name description r/w default 31:0 lladdr load linked address r unpred watchlo cp0 register 18, select 0 bit31302928272625242322212019181716151413121110 9 8 7 6 5 4 3 2 1 0 vaddr 0 r w def.xxxxxxxxxxxxxxxxxxxxxxxxxxxxx0 0 0 bits name description r/w default 31:3 vaddr the virtual address to match r/w unpred 1 r if this bit is a one, then watch e xceptions are enabled for loads that match the address. r/w 0 0 w if this bit is a one, then watch exc eptions are enabled for stores that match the address. r/w 0 iwatchlo cp0 register 18, select 1 bit31302928272625242322212019181716151413121110 9 8 7 6 5 4 3 2 1 0 vaddr i 0 0 def.xxxxxxxxxxxxxxxxxxxxxxxxxxxxx0 0 0 bits name description r/w default 31:3 vaddr the virtual address to match r/w unpred 2 i if this bit is a one, then watch e xceptions are enabled for instruction accesses that match the address. r/w 0
36 amd alchemy? au1000? processor data book - preliminary cpu 30360d 2.7.20 data watchhi register (cp0 register 19, select 0) the watchlo and watchhi registers are the interface to the data watchpoint facility. 2.7.21 instruction watchhi register (cp0 register 19, select 1) the iwatchlo and iwatchhi registers are the inte rface to the instruction watchpoint facility. 2.7.22 scratch register (cp0 register 22, select 0) the scratch register exists for the convenience of software. upon a read, this register returns the value last written into it. watchhi cp0 register 19, select 0 bit31302928272625242322212019181716151413121110 9 8 7 6 5 4 3 2 1 0 mg 0 asid 0 mask 0 def.1x000000xxxxxxxx0000xxxxxxxxx000 bits name description r/w default 31 m another pair of watch registers is implemented at the next select index. r1 30 g if this bit is one, then the asid field is ignored and any address that matches causes a watch exception. r unpred 23:16 asid asid value which is required to match that in the entryhi register if the g bit is zero in the watchhi register. r/w unpred 11:3 mask any bit in this field that is a one inhibits the corresponding address bit from participating in the address match. r/w unpred iwatchhi cp0 register 19, select 1 bit31302928272625242322212019181716151413121110 9 8 7 6 5 4 3 2 1 0 0g 0 asid 0 mask 0 def.0x000000xxxxxxxx0000xxxxxxxxx000 bits name description r/w default 30 g if this bit is one, then the asid field is ignored and any address that matches causes a watch exception. r unpred 23:16 asid asid value which is required to match that in the entryhi register if the g bit is zero in the watchhi register. r/w unpred 11:3 mask any bit in this field that is a one inhibits the corresponding address bit from participating in the address match. r/w unpred scratch cp0 register 22, select 0 bit31302928272625242322212019181716151413121110 9 8 7 6 5 4 3 2 1 0 scratch def.xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx bits name description r/w default 31:0 scratch this register is present for the convenience of software. r/w unpred
amd alchemy? au1000? processor data book - preliminary 37 cpu 30360d 2.7.23 debug register (cp0 register 23, select 0) the debug register is part of the interface to the ejtag facility. 2.7.24 depc register (cp0 register 24, select 0) the depc register is part of the interface to the ejtag facility. 2.7.25 data cache tag register (cp0 register 28, select 0) the dtag and ddata registers are the interface to the data cache array. this cache interface is unique to the au1. note: this register corresponds to the taglo regi ster in the mips32 isa specification. debug cp0 register 23, select 0 bit313029282726252423222120191817161514131211109876 5 43210 dbd dm 0 lsnm 0 001 dexccode 0 sst 0 0 dint 0dbpdss def.0 0 0 0 00000000000 0 1xxxxx0 0 0 0 0 0 0000 bits name description r/w default 31 dbd debug exception in branch delay slot. r unpred 30 dm if this bit is a one, then in debug mode. r 0 28 lsnm load/stores are performed in the normal fashion when in debug mode. r/w 0 17:15 001 ejtag version 2.5 r 001 14:10 dexccode cause[exccode] for normal exceptions in debug mode. r unpred 8 sst enable single step mode r/w 0 5 dint last debug exception was asynchronous debug interrupt r 0 1 dbp last debug exception was an sdbpp instruction r 0 0 dss last debug exception was a single step r 0 depc cp0 register 24, select 0 bit31302928272625242322212019181716151413121110 9 8 7 6 5 4 3 2 1 0 depc def.xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx bits name description r/w default 31:0 depc debug exception program counter. r/w unpred dtag cp0 register 28, select 0 bit31302928272625242322212019181716151413121110 9 8 7 6 5 4 3 2 1 0 tag m ru nmru lru 0 0dslv def.xxxxxxxxxxxxxxxxxxxxxxxxxx0 0xxxx bits name description r/w default 31:12 tag tag represents bits [31:12] of a physical memory address. bits [35:32] of the physical address are always zero. r/w unpred 11:10 mru most recently used way. r/w unpred 9:8 nmru next most recently used way. r/w unpred 7:6 lru least recently used way. r/w unpred 3 d cache line is dirty (modified). r/w unpred 2 s cache line is shared (for data cache snoops). r/w unpred 1 l locked. this bit is set by the user to prevent overwriting of the cache line. r/w unpred 0 v cache line valid. r/w unpred
38 amd alchemy? au1000? processor data book - preliminary cpu 30360d 2.7.26 data cache data register (cp0 register 28, select 1) the dtag and ddata registers are the interface to the data cache array. note: this register corresponds to the datalo re gister in the mips32 isa specification. 2.7.27 instruction cache tag register (cp0 register 29, select 0) the itag and idata registers are the interface to the instruct ion cache array. this cache interface is unique to the au1. note: this register corresponds to the taghi r egister in the mips32 isa specification. ddata cp0 register 28, select 1 bit31302928272625242322212019181716151413121110 9 8 7 6 5 4 3 2 1 0 data def.xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx bits name description r/w default 31:0 data data from the data cache line. r unpred itag cp0 register 29, select 0 bit31302928272625242322212019181716151413121110 9 8 7 6 5 4 3 2 1 0 tag m ru nmru lru 0lv def.xxxxxxxxxxxxxxxxxxxxxxxxxx0 0 0 0xx bits name description r/w default 31:12 tag tag represents bits [31:12] of a physical memory address. bits [35:32] of the physical address are always zero. r/w unpred 11:10 mru most recently used way. r/w unpred 9:8 nmru next most recently used way. r/w unpred 7:6 lru least recently used way. r/w unpred 1 l locked. this bit is set by the user to prevent overwriting of the cache line. r/w unpred 0 v cache line valid. r/w unpred
amd alchemy? au1000? processor data book - preliminary 39 cpu 30360d 2.7.28 instruction cache data register (cp0 register 29, select 1) the itag and idata registers are the inte rface to the instruction cache array. note: this register corresponds to the datahi re gister in the mips32 isa specification. 2.7.29 errorepc register (cp0 register 30, select 0) the errorepc register is a required register for exception processing. 2.7.30 desave register (cp0 register 31, select 0) the desave register is part of the interface to the ejtag facility. idata cp0 register 29, select 1 bit31302928272625242322212019181716151413121110 9 8 7 6 5 4 3 2 1 0 data def.xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx bits name description r/w default 31:0 data data from the instruction cache line. r unpred errorepc cp0 register 30, select 0 bit31302928272625242322212019181716151413121110 9 8 7 6 5 4 3 2 1 0 errorepc def.xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx bits name description r/w default 31:0 errorepc error exception program counter r/w unpred desave cp0 register 31, select 0 bit31302928272625242322212019181716151413121110 9 8 7 6 5 4 3 2 1 0 desave def.xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx bits name description r/w default 31:0 desave debug save scratch register, for debug handlers. r/w unpred
40 amd alchemy? au1000? processor data book - preliminary cpu 30360d 2.8 system bus the au1 core communicates with memories and peripherals via the system bus (s bus). the system bus is a 36-bit physi- cal address and 32-bit data bus which is internal to the au1000 processor. the system bus is the coherency point within the au1000 processor. 2.8.1 sbus arbitration the system bus supports multiple masters?the au1 core and peripheral dma engines. the system bus is granted to the masters in a least-recently-used/fair sc heme. this scheme prevents two or more masters from consuming the entire sys- tem bus bandwidth, while permitting low latency access to the system bus for masters which request the bus infrequently (such as peripherals). the system bus requestors in the au1000 processor are: au1 core ethernet mac controller (2) usb host controller irda controller dma controller the au1 presents a single request to the system bus arbiter fo r the three possible requestors: the data cache, the instruc- tion cache and the write buffer. the data cac he has the highest priority and the write buffer the lowest priority among the three requests. however, the write buffer priority becomes th e highest when the data cache requests a load to an address in the write buffer to allow the write buffer to empty prior to fulfilling the data cache load. the system bus arbiter has four bus arbitrat ion slots for ha ndling the system bus masters: slot 0: au1 core (data cache, instruction cache, write buffer) slot 1: ethernet mac controllers slot 2: dma controller slot 3: usb host controller and irda controller the arbitration scheme for the syst em bus is round-robin; that is, each bus mast er slot has an equal opportunity to obtain access to the system bus. for a particular system bus master x, if no other system bus master s request the bus, then bus master x immediately wins the system bus. by contrast, if all other system bus masters request the bus, then bus master x must wait for three other system bus master slots to transfer before it wins the system bus, as shown in figure 2-4 on page 40. figure 2-4. system bus arbitration when a system bus master wins arbitration of the system bus, it performs transfers to/fro m the integrated peripherals, sdram, or the static bus. a b c x req a req b req c req x sbus
amd alchemy? au1000? processor data book - preliminary 41 cpu 30360d 2.8.2 sbus coherency model the sbus is the coherency point within the au1000 processor. an sbus master (i.e. au1 core or peripheral dma engine) marks each sbus transaction as either coherent or non-c oherent. sbus transactions marked as coherent are then snooped by all caching masters (i.e. au1 data cache). an sbus transaction that is marked non-coherent is not snooped by caching masters. the au1 core is a coherent, caching master. the au1 data cac he snoops sbus transactions; if a read transaction hits in the data cache then the data cache provid es the data, if a write transaction hits in the data cache then the data cache array is updated with the new data. the integrated peripherals (with dma engines) can be configur ed for coherent or non-coherent o peration. the ?c? bit in the peripheral/module enable register directs whether peripheral sbus transactions are to be marked coherent or non-coher- ent. if a peripheral is configured for coherent operation, then it is not necessary to writeback and invalidate au1 data cache lines which hit in the memory buffers used by dma engines. if, on the other hand, the peripheral is configured for non- coherent operation, then softwar e must ensure that memory buffers used by the dma engines are not in the data cache (else the data cache and/or the memory buffer may contain old, stale data). the decision to use, or not use, coherent sbus transactions is left to the application. however, peripheral device drivers using coherent sbus transactions will perform better than drivers not using coherent sbus transactions since the need to writeback the data cache is eliminated. 2.9 ejtag ejtag is supported per the mips ejtag re v. 2.5 specification. ejtag provides for cpu and board level bring-up and debug.
42 amd alchemy? au1000? processor data book - preliminary cpu 30360d
amd alchemy? au1000? processor data book - preliminary 43 3 memory controllers 30360d 3.0 memory controllers the au1000 processor contains two memory controllers, one for sdram and one for static devices. the sdram controller supports sdram, smrom and sync flash. the static device controller supports sram, flash, rom, page mode rom, pcmcia/compact flash devices, and an external lcd controller interface. both memory controllers support software configurable me mory address spaces. this allows designers to keep memory regions contiguous. for example, a system with 4 mb initially in stalled would locate the memory at physical address 0. nor- mally, adding 16 mb would create a 12 mb gap in the memory map. with the address configuration options in the au1000 the 4 mb can be relocated to start at 16 mb, and the new memo ry can be located at 0 to allow a 20 mb contiguous memory pool. all registers in the memory controller block are located off of the base address shown in table 3-1. the system designer has the choi ce of booting from 32-bi t flash, 16-bit flash, 32-bit smrom, and 32-bit syncflash. the romsel and romsize configuration is discussed in more det ail in section 8.3 "boot" on page 198. table 8-1 "romsel and romsize boot device" on page 198 shows how the stat e of romsel and romsize determines where the proces- sor boots from. table 3-1. memory controller block base address name physical base address kseg1 base address mem 0x0_1400_0000 0x_b400_0000
44 amd alchemy? au1000? processor data book - preliminary sdram memory controller 30360d 3.1 sdram memory controller the sdram memory controller of the au1000 processor is designed for glueless interface to one, two, or three ranks of sdram or smrom. sdram and syncflash ar e run at 1/2 the internal system bus speed. the system bus defaults to 1/2 the processor clock speed so that sdram or syncflash wi ll run at 99 mhz with a 396 mhz au1000. smrom operates at 1/4 the speed of the system bus. the system bus divider is programmable, see section 7.4.3 "device power management - sleep" on page 190 for more information. the sdram interface supports three chip selects (sdcs[2:0]#), corresponding to three ranks of sdram. each chip select can be configured to support either sdram or smrom. in add ition, chip select 0 can be configured for syncflash (no other chip selects can be used to support syncflash). for ch ip selects configured as sdram or syncflash (on chip select 0) the controller keeps one row open for up to four banks per chip select allowing fast accesses and reducing the need to issue precharge cycles. note: the sdram memory controller supports a maximum of two loads per chip select. when resetin# is negated, code is fetc hed from smrom/syncflash if smrom/sy ncflash boot is selected. when using smrom or syncflash for boot, the smromcke signal sh ould be used for the smrom/syncflash cke. if smrom or syncflash are being used (but not for boot), sdcke should be used for the clock enable. after boot internal configuration registers can be written to enable sdram chip sele cts. when a chip select is enabled the sdcke is driven asserted and clocks are started. software mu st wait 10 s for the sdram clock to stabilize before any device specific initialization steps. all sdram/smrom ranks must be 32 bits wide. support is in cluded for sdram with 2 or 4 banks, 11 to 13 row address bits, and 7 to 11 column address bits. it is also possible to send explicit commands to the sdram, under software control, for diagnostic, initialization, or power management purposes. sdram clocks keep running during a runtime reset to allow any transaction in progress to complete. this avoids the possi- bility of bus contention when t he part is brought out of reset. note that the sdram controller assumes the following external sdram configuration: burst length = 8 addressing mode = sequential write mode = burst read and write
amd alchemy? au1000? processor data book - preliminary 45 sdram memory controller 30360d 3.1.1 sdram controller programming model the sdram controller contains a number of registers which co nfigure the operation of the in terface. all registers in the sdram controller block are located off of the base address shown in table 3-1 "memory controller block base address" on page 43. table 3-2 shows the memory map of the register block. 3.1.2 sdram registers each chip select is configured by two registers, a mode register and an addr ess configuration register. 3.1.2.1 chip select mode configuration registers the format and reset values of the chip select mode configur ation registers is shown in the following figure. the timing parameters (tcl, tcrd, trp, twr, tmrd, and tras) correspond di rectly to times shown in the sdram timing diagrams. times are measured in sdram/smrom clock cycles. the default values for chip select zero correspond to values for smrom operation. chip select 1 and 2 are configured with the slowest timing values at reset. reserved fields should be written as zeros and ignored on read to preserve compatibility wit h future versions of the prod- uct. table 3-2. sdram configuration registers offset from 0x0_1400_0000 (physical) 0x_b400_0000 (kseg1) register name description 0x0000 mem_sdmode0 sdram chip select n (sdcs n #) mode configuration register (tim- ing and functionality) 0x0004 mem_sdmode1 0x0008 mem_sdmode2 0x000c mem_sdaddr0 sdcs n # address configuration and enable 0x0010 mem_sdaddr1 0x0014 mem_sdaddr2 0x0018 mem_sdrefcfg refresh configuration and timing 0x001c mem_sdprecmd issue precharge to all enabled sdram chip selects 0x0020 mem_sdautoref issue auto refresh to all enabled sdram chip selects 0x0024 mem_sdwrmd0 write data to sdcs n # sdram mode configuration register 0x0028 mem_sdwrmd1 0x002c mem_sdwrmd2 0x0030 mem_sdsleep force sdra m into self refresh mode 0x0034 mem_sdsmcke toggle smromcke pin mem_sdmode0 - cs0 mode configuration offset = 0x0000 bit31302928272625242322212019181716151413121110 9 8 7 6 5 4 3 2 1 0 sf f sr bs rs cs tras tmrd twr trp trcd tcl def.00000000001010000111111111101100 mem_sdmode1 - cs1 mode configuration offset = 0x0004 mem_sdmode2 - cs2 mode configuration offset = 0x0008 bit31302928272625242322212019181716151413121110 9 8 7 6 5 4 3 2 1 0 fsrbs rs cs tras tmrd twr trp trcd tcl def.00000000000101001111111111111111
46 amd alchemy? au1000? processor data book - preliminary sdram memory controller 30360d bits name description r/w default 31:24 ? reserved. should be cleared. r 0 23 sf selects syncflash operation. syncflash is available only on sdcs0#. for other chip selects, this bit is reserved and should be cleared. 0 syncflash is not being used. 1 syncflash is being used. note: syncflash support is available star ting with silicon revision 2.3, also known as silicon stepping ?hc?. for silic on revisions 2.2 and earlier, this bit is reserved and should be cleared. r/w 0 22 f setting the f bit allows the sdram controller to assume that no caching master except the core will access this memory space. this allows accesses to begin sooner. note that the cpu core is the only possi ble caching master, so it is safe for the system designer to set this bit. r/w 0 21 sr chip select operating mode 0 sdram/syncflash operation 1 smrom operation r/w see above 20 bs select number of banks 0 chip select controls 2-bank sdram 1 chip select controls 4-bank sdram note: this bit must be cleared for smrom support. r/w see above 19:18 rs this field sets the number of bi ts in the row address as shown below: rs row address size 00 11 01 12 10 13 11 reserved r/w see above 17:15 cs this field sets the number of bi ts in the column address as shown below: cs column size 000 7 001 8 010 9 011 10 100 11 all other values are reserved. r/w see above 14:11 tras this field designates the minimum delay from a activate to a precharge com- mand. (tras + 1) is the actual number of clock cycles. r/w 15 10:9 tmrd this field sets the required delay from an external load of the sdram mode register (not the chip select mode register) to an activate command. (tmrd + 1) is the actual number of clock cycles. r/w 3 8:7 twr the twr field sets the write recovery time. this is the last data for a write to a precharge. this field is so metimes referred to a tdpl. (twr + 1) is the actual number of clock cycles. r/w 3 6:5 trp this field sets the time from precharge to the next activate command. (trp + 1) is the actual number of clock cycles. r/w 3 4:3 trcd this field sets the ras to cas delay. (trcd + 1) is the actual number of clock cycles. r/w see above 2:0 tcl this field sets the minimum cas latenc y timing. this is the time from cas to data on reads. (tcl + 1) is the actual number of clock cycles. r/w see above
amd alchemy? au1000? processor data book - preliminary 47 sdram memory controller 30360d 3.1.2.2 sdram chip select address configuration regi sters (mem_sdaddr n ) the sdram chip-select address configuration registers ( mem_sdaddr n ) assign an address range for each chip select. as shown below, each register contains a base addre ss, an address comparison mask, and an enable bit. once enabled (e bit set), a chip select is asserted when the following condition is met: (phys_addr & addr_mask) == base_addr where phys_addr: 32-bit physical addre ss output on the internal system bus (from the tlb for memory-ma pped regions) (bits 35:32 of the physical address are zeros.) addr_mask: address comparison mask taken from csmask base_addr: chip select base address taken from csba chip select regions must be programmed so that each chip select occupies a unique area of the physical address space. programming overlapping chip select regions results in undefined operation. mem_sdaddr0 - sdcs0# address configuration offset = 0x000c bit31302928272625242322212019181716151413121110 9 8 7 6 5 4 3 2 1 0 e csba csmask def.00000000000rs00011111111111111111 mem_sdaddr1 - sdcs1# address configuration mem_sdaddr2 - sdcs2# address configuration offset = 0x0010 offset = 0x0014 bit31302928272625242322212019181716151413121110 9 8 7 6 5 4 3 2 1 0 e csba csmask def.00000000000011111111111111111111 bits name description r/w default 31:21 ? reserved. should be cleared. r 0 20 e enable. 0 chip select is disabled. 1 chip select is enabled. r/w 0, except for mem_sdaddr0 (note 1) note 1. the e bits for the chip selects sdcs1# and sdcs2# are aut omatically cleared (disabled) co ming out of a runtime or hardwa re reset. for sdcs0, however, the reset value of the e bit depends on romsel and romsize: sdcs0#?s e bit is set when the romsel and romsize pins indicate that the smrom/sync flash should be used for the boot vector (romsel==1, rom- size==0). see also section 8.3 "boot" on page 198. 19:10 csba chip select base address. specifies bits 31:22 of the phys ical base address for this chip select. (the lower bits of the base address are zero.) r/w 0x3ff, except for mem_sdaddr0 where the default value is 0x7f. 9:0 csmask chip select address mask. specifies which bits of csba ar e used to decode this chip select. r/w 0x3ff
48 amd alchemy? au1000? processor data book - preliminary sdram memory controller 30360d 3.1.2.3 refresh conf iguration register the refresh configuration register sets th e timing of sdram refresh for all chip selects. since the timing for these signals apply to all chip selects, if different types of sdram is us ed the worst case timing must be applied. the format of the refresh configuration register is as follows: 3.1.2.4 precharge al l command register writing any value to the mem_sdprecmd register issues a precharge all comma nd to all enabled sdram chip selects. this can be used for initialization sequenc es that require certain operations to be performed in a deterministic order. reading from the mem_sdprecmd register is unpredictable. mem_sdrefcfg - refresh configuration offset = 0x0018 bit31302928272625242322212019181716151413121110 9 8 7 6 5 4 3 2 1 0 tr c tr p r e r i def.11111101111111111111111111111111 bits name description r/w default 31:28 trc the trc field specifies the minimum time from the start of an auto refresh cycle to an activate command for all sdram chip selects. (trc + 1) is the actual number of clock cycles. r/w 0xf 27:26 trpm this field specifies the minimum ti me from a precharge to the start of a refresh cycle for all sdram chip sele cts. this is used because a precharge all command is automatically initiat ed before an auto refresh command. this value should be programmed with the worst case trp from the sdr_csmode n registers. (trpm + 1) is the actual number of clock cycles. r/w 3 25 e when this bit is set, refresh is enab led for all chip selects configured as sdram. r/w 0 24:0 ri refresh interval - this field specifie s the maximum refresh interval in system bus clocks for all sdram ranks. the refresh interval is for each individual refresh so for a system with a row address size of 12 (4096 rows) and memory with a refresh time of 64 ms (all rows), the individual refresh interval will be 15.7 s (64 ms/4096). with a sys- tem bus clock of 198 mhz, the ri value should be 0xc24 (15.7 s / (1/198 mhz). r/w 0x1ffffff mem_sdprecmd - precharge all command reg offset = 0x001c bit31302928272625242322212019181716151413121110 9 8 7 6 5 4 3 2 1 0 pa def.xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx bits name description r/w default 31:0 pa writing any value to pa will caus e a precharge command to be issued to all enabled sdram chip selects. w unpred
amd alchemy? au1000? processor data book - preliminary 49 sdram memory controller 30360d 3.1.2.5 auto refresh command register writing to the mem_sdautoref register performs an auto refresh command on all enabled sdram chip selects. this can be used for initialization sequences that require specific operations to be perfor med in a deterministic order. to insure future compatibility the value written should always be zero. reading from the mem_sdautoref register will return the current value of the refresh timer. 3.1.2.6 external sdram mode register access the mem_sdwrmd0 , mem_sdwrmd1 , and mem_sdwrmd2 command registers allow software to directly write to the mode registers in sdram connected to each chip select. this can be used in initialization s equences that require certain operations be performed in a deterministic order. 3.1.2.7 sdram sleep/self refresh command register writing any value to this register performs sends a self refresh command on all enabled sdram chip selects. this com- mand can be used for the sdram power-down sequence which requires specific commands to be performed in a deter- ministic order. after performing self refresh the sdram co ntroller will hold sdcke low and wait until a sleep exit sequence or reset is per- formed. for this reason nothing should access the sdram after this command has been issued. mem_sdautoref - auto refresh command offset = 0x0020 bit31302928272625242322212019181716151413121110 9 8 7 6 5 4 3 2 1 0 ar def.xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx bits name description r/w default 31:0 ar writing a value to ar causes an au to refresh command to be issued to all enabled sdram chip selects. r/w unpred mem_sdwrmd0 - write cs0 sdram mode offset = 0x0024 mem_sdwrmd1 - write cs1 sdram mode offset = 0x0028 mem_sdwrmd2 - write cs2 sdram mode offset = 0x002c bit31302928272625242322212019181716151413121110 9 8 7 6 5 4 3 2 1 0 ba wm def.xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx bits name description r/w default 31:30 ba[1:0] bank address. these bits are re flected on the sdba[1:0] signals. they can be used to write to the extended mode register (for synchronous flash and battery ram, for example). these bits must be cleared otherwise. w unpred 29:0 wm the value written to this register is written to the external sdram mode reg- ister for the corresponding chip select. w unpred mem_sdsleep -sdram sleep offset = 0x0030 bit31302928272625242322212019181716151131211109876543210 sl def.xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx bits name description r/w default 31:0 sl writing any value to sl will issue a self refresh command on all enabled chip selects. w unpred
50 amd alchemy? au1000? processor data book - preliminary sdram memory controller 30360d 3.1.2.8 smromcke toggle register writing to this register causes the state of the smromcke signal to change. smromcke will default to high when boot- ing from smrom or sync flash. this is used during power- up configuration to change the smrom burst size from 4 to 8 beats. this command register does not affect the sdram sdcke signal. 3.1.3 sdram timing the following figures show examples of typical read, typical write and refresh timing. figure 3-1. sdram typical read timing mem_sdsmcke -smromcke toggle offset = 0x0034 bit31302928272625242322212019181716151413121110 9 8 7 6 5 4 3 2 1 0 st def.xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx bits name description r/w default 31:0 st writing to st (regardless of the value written) inverts the current state of smromcke. w unpred row col (a) col (b) row (c) col (c) row (d) a1 b1 b2 c1 c2 c3 c4 activate read read precharge activate read sdclk[n] sdcke sdcs[n]# sdras# sdcas# sdwe# sdba[1:0] sda[12:0] sdqm# sdd[31:0] (a/b) tr a s tr c d activate tr p tcl (1 beat) (2 beat) (4 beat) the above timing represents the following: 1) tras = 4 (5 sdram clock cycles) 2) trp = 0 (1 sdram clock cycles) 3) trcd = 1 (2 sdram clock cycles) 4) tcl = 1 (2 sdram clock cycles) 5) tmrd = 0 (2 sdram clock cycles) the above timing is presented to concisely display the different sdram timing parameters. the functional bus behavior may differ from that displayed. tmrd mode register set
amd alchemy? au1000? processor data book - preliminary 51 sdram memory controller 30360d figure 3-2. sdram typical write timing figure 3-3. sdram refresh timing row col (a) col (b) row (c) col (c) row (d) a1 b1 b2 c1 c2 activate write (1 beat) write (2 beat) activate write (2 beat) precharge activate sdclk[n] sdcke sdcs[n]# sdras# sdcas# sdwe# sdba[1:0] sda[12:0] sdqm# tr a s tr c d tw r tr p mode tmrd register set the above timing represents the following: 1) tras = 4 (5 sdram clock cycles) 2) trp = 0 (1 sdram clock cycles) 3) trcd = 1 (2 sdram clock cycles) 4) tmrd = 0 (1 sdram clock cycles) the above timing is presented to concisely display the diff erent sdram timing parameters. the functional bus behavior may differ from that displayed. (a/b) sdd[31:0] sdclk[2:0] sdcke sdcs[2:0]# cmd auto refresh activate precharge all tr c tr p m this example assumes that all sdclk ranks ([2:0]) are enabled. the above timing represents the following: 1) trpm = 3 (4 sdram clock cycles) 2) trc = 3 (4 sdram clock cycles)
52 amd alchemy? au1000? processor data book - preliminary sdram memory controller 30360d 3.1.4 sdram hardware considerations table 3-3 shows the signals associated with the sdram interface. table 3-3. sdram signals signal input/ output description sda[12:0] o address outputs. a0-a12 are driven during the active command (row-address a0- a12) and read / write command to select one location out of the memory array in the respective bank. the address outputs also provide the opcode during a load mode register command. sdba[1:0] o bank address outputs. sdba1 and sdba0 define to which bank the active , read , write or precharge command is being applied. the sdba signal values are pro- grammed in mem_sdwrmd n [ba]. sdd[31:0] io sdram data bus sdqm[3:0]# o input/output mask. sdqm# is a mask signal for write accesses and an output enable signal for read accesses. sdqm0# ma sks sdd[7:0], sdqm1# masks sdd[15:8], sdqm2# masks sdd[23:16], sdqm3# masks sdd[31:24]. sdras# o command outputs. sdras#, sdcas# and sdwe# (along with sdcs n #) define the command being sent to the sdram rank. sdcas# o sdwe# o sdclk[2:0] o clock output corresponding to each of the three chip selects. clock speed is 1/2 sys- tem bus frequency when corresponding sdcs n # is set to sdram or syncflash, 1/4 system bus frequency when corresponding sdcs n # is set to smrom. sdcs[2:0]# o programmable ch ip selects (3 ranks). sdcke o clock enable for sdram. smromcke o synchronous mask rom clock enable. this signal must be pulled high if the system is booting from smrom. muxed with gpio[6]. if romsel and roms ize are configured to boot from synchro- nous mask rom, smromcke will control the pin out of reset, else gpio[6] will con- trol the pin out of reset.
amd alchemy? au1000? processor data book - preliminary 53 static bus controller 30360d 3.2 static bus controller the static bus controller provides a general purpose interfac e to a variety of external peripherals and memory devices. each of the four static bus chip selects may be progra mmed to support standard flash memory, rom, page mode flash/ rom, sram, i/o peripherals, pcmcia/compact flash devices, or an lcd controller. because of the similarity of compact flash and pcmcia, references to pcmcia should be tak en as applicable to compact flash except where noted. the au1000 processor allows control of different device ty pes by reconfiguring what co ntrol signals chip select n manages based on how the device type field (dty) is encoded in the mem_stcfg n register. all device types use the same address and data bus signals, rad[31:0] a nd rd[31:0]. descriptions of all device types are provided in section 3.2. 2 "static ram, i/o device and flash device types" on page 60, section 3.2.3 "pcmcia/compact flash device type" on page 63, and section 3.2.4 "lcd controller device type" on page 69. a read to the static bus causes a 32-bit access. this can cause a potential problem with volatile devices because a single 16-bit read results in two 16-bit reads on the external bus. chip selects may be programmed for fixed access times or an external wait signal may be used to provide a variable delay per access. while the static bus controller is a synchronous device internally , no external clock is available to reference the control sig - nals. the internal cl ock comes from the system bus cloc k. configuring the system bus cloc k determines the internal refer- ence for the static controller and associated timings. 3.2.1 static controller programming model the properties of each static cont roller chip select are determined by a set of registers. all registers in the static controll er block are located off of the base address shown in table 3-1 "memory controller block base address" on page 43. table 3-4 shows the registers and offsets for the static bus controller. after modifying the configuration of a chip select, softwa re must issue a sync instruction before write accesses to the chip select are allowed. table 3-4. static bus controller configuration registers offset from 0x0_1400_0000 (physical) 0x_b400_0000 (kseg1) register name description 0x1000 mem_stcfg0 configuration for rcs0#. 0x1004 mem_sttime0 timing parameters for rcs0#. 0x1008 mem_staddr0 address region control for rcs0#. 0x1010 mem_stcfg1 configuration for rcs1#. 0x1014 mem_sttime1 timing parameters for rcs1#. 0x1018 mem_staddr1 address region control for rcs1#. 0x1020 mem_stcfg2 configuration for rcs2#. 0x1024 mem_sttime2 timing parameters for rcs2#. 0x1028 mem_staddr2 address region control for rcs2#. 0x1030 mem_stcfg3 configuration for rcs3#. 0x1034 mem_sttime3 timing parameters for rcs3#. 0x1038 mem_staddr3 address region control for rcs3#.
54 amd alchemy? au1000? processor data book - preliminary static bus controller 30360d 3.2.1.1 static bus configuration registers the static bus configuration registers ( mem_stcfgn ) configure the basic properties of each chip select. support is included for static ram, flash, rom, pcmcia, lcd, and other types of i/o devices. when programming a chip select as an i/o, lcd, or pcmc ia device the address comparison mask will expect an address with the upper nibble set as shown in table 3-5 "device type encoding" on page 55 for the different device types. the tlb must be set up accordingly to map ad dresses to the memory region capt ured by the associ ated chip select. for example, to configure the tlb for use with an lcd contro ller, bits 29:26 of coprocesso r register entry lo must be 0b1110 (in addition to the other steps necessary to set up t he tlb). these bits represent add ress bits 35:32 of the physical address which must be 0xe in order for the address to match successfully when a chip select is enabled as an lcd device. since the ram and flash have an upper nibble of zero, it is not necessary to use the tlb to access devices set up with these types. mem_stcfg0 offset = 0x1000 bit31302928272625242322212019181716151413121110 9 8 7 6 5 4 3 2 1 0 bv d5 av be ts ew h bs pm ro dty def.0000000000000000000000000rs000011 mem_stcfg1 mem_stcfg2 mem_stcfg3 offset = 0x1010 offset = 0x1020 offset = 0x1030 bit31302928272625242322212019181716151413121110 9 8 7 6 5 4 3 2 1 0 be ts ew h bs pm ro dty def.00000000000000000000000000000000 bits name description r/w default 31:13 ? reserved. should be cleared. r 0 12 bv burst size visible. when this bi t is set the burst size for static transfers will be output for chip selects not configured as lcd or pcmcia. the burst size output is one less than the number of 32-bit words to be transferred. for 16-bit chip selects twice as many beats will occur. the ma pping of the burst size to pins is shown in table 3-6 "burst size mapping" on page 55. this bit is a global attribute and is present only in mem_stcfg0 . r/w 0 11 d5 divide by 5. setting this bit wi ll divide the system bus clock by 5 to generate lclk. when d5 is cleared the system bus clock is divided by 4 to generate lclk. this bit is a global attribute and is present only in mem_stcfg0 . r/w 0 10 av address visible. setting this bit will place the address for all internal accesses to the system bus on the static address bus. this is intended to be used as a debug aid and should not be used during normal operation as it will increase system power usage. this bit is a global attribute and is present only in mem_stcfg0 . r/w 0 9 be endianness. 0 little endian 1 big endian program this bit to match the endianness of the processor. this bit should not be set for pcmcia. r/w 0 8 ts time scale for chip select timing parameters. 0 do not scale the timing parameters. 1 multiply the timing parameters by a factor of four. this option allows for longer access times. r/w 0
amd alchemy? au1000? processor data book - preliminary 55 static bus controller 30360d 7 ew when the ew bit is set the ewait# input is allowed to stretch the bus access time. the ew bit does not apply to chip selects operating in lcd or pcmcia m ode because they have differ- ent wait mechanisms. r/w 0 6 h half bus. selects the data bus width for the chip select. 0 32-bit bus 1 16-bit bus using bits 15:0 of the data bus. note: the h bit does not apply for pcmcia and lcd device types and must be cleared for these device types. r/w 0, except for mem_stcfg0 where the default value is determined by romsel and romsize out of reset. see table 8- 1 on page 198. 5 bs burst size for page mode accesses. selects the burst size for page mode accesses. valid only in page mode (pm=1). 0 4 beats 1 8 beats r/w 0 4 pm if the pm bit is set the chip select will operate in page mode. this allows quick access to sequential locations in memory. page mode applies only to reads. see section 3.2.5.1 "page mode transfers" on page 71. r/w 0 3 ro if the ro bit is set the chip select will operate in read only mode. this will inhibit the generation of write cycles to the chip select. any attempt to write to the address region controlled by a read only chip select will be ignored. r/w 0 2:0 dty device type. selects the type of device controlled by the static controller chip select. a list of device types and encodings is shown in table 3-5 "device type encoding". programming multiple chip selects as lcd or pcmcia is ille- gal. only one of each is supported. r/w 0 (sram), except for mem_stcfg0 where the default value is 3 (flash). table 3-5. device type encoding dty chip select function pfn[35:32] (upper nibble of physical address) reference 0 static ram 0x0 section 3.2.2 1 i/o device 0xd section 3.2.2 2 pcmcia device/compact flash 0xf section 3.2.3 3 flash memory 0x0 section 3.2.2 4 lcd device 0xe section 3.2.4 5?7 reserved table 3-6. burst size mapping signal pin burst_size[2] lwr0# burst_size[1] lrd1# burst_size[0] lrd0# bits name description r/w default
56 amd alchemy? au1000? processor data book - preliminary static bus controller 30360d 3.2.1.2 static timing registers the static timing registers allow software to control the timing of each phase of a static bus access. the names of the tim- ing parameters correspond directly to timing parameters shown on the timing diagrams. all timing parameters are expressed as a number of cloc k cycles. the base clock frequ ency is the system bus clock. the actual number of clocks for each timing parameter (t parameter ) is shown in table 3-7. note that the timing behavior for tcsh is different and is shown in table 3-8. table 3-7. actual number of clocks for timing parameters (except tcsh) device type ts = 0 ts = 1 static ram, i/o, flash t parameter + 1 (4 * t parameter ) + 1 pcmcia device/compact flash t parameter + 2 (4 * t parameter ) + 2 table 3-8. actual number of clocks for tcsh tcsh value ts=0 ts=1 0000 3 3 0001 3 6 0010 6 12 0011 6 15 0100 6 18 0101 9 24 0110 9 27 0111 9 30 1000 12 36 1001 12 39 1010 12 42 1011 15 48 1100 15 51 1101 15 54 1110 18 60 1111 18 63
amd alchemy? au1000? processor data book - preliminary 57 static bus controller 30360d mem_sttime0 (i/o, flash, sram config) offset = 0x1004 bit31302928272625242322212019181716151413121110 9 8 7 6 5 4 3 2 1 0 twcs tcsh tw p t c sw t p m ta def.11111111111111111111111111011101 mem_sttime1 (i/o, flash, sram config) mem_sttime2 (i/o, flash, sram config) mem_sttime3 (i/o, flash, sram config) offset = 0x1014 offset = 0x1024 offset = 0x1034 bit31302928272625242322212019181716151413121110 9 8 7 6 5 4 3 2 1 0 twcs tcsh tw p t c sw t p m ta def.11111111111111111111111111111111 bits name description r/w default 31 ? reserved. should be cleared. r 0 30:28 twcs this field specifies the required chip select hold time after a write pulse. see table 3-7 on page 56 for the ac tual number of clock cycles. this field applies only to chip selects configured to support flash memory. for all other modes this timing parameter is one cycle regardless of the va lue in the twcs field. r/w 0x3 27:24 tcsh chip select hold-off. specif ies the minimum number of cycles that the chip select must remain inactive between accesses. the next transaction through the static bus controller is held off until the tcsh parameter is satisfied. if this next access falls within another chip select?s memory region, the new set of tim- ing parameters associated with t he controlling chip select take effect once the new transaction begins. note that the system bus can arbitrarily extend the time between accesses for internal operations. this can add up to about five additional clocks to the programmed time. see table 3-8 on page 56 for the ac tual number of clock cycles. r/w 0xf 23:20 ? reserved. should be cleared. r 0 19:14 twp this field specifies the duration of the write enable. see table 3-7 on page 56 for the ac tual number of clock cycles. r/w 0x3f 13:10 tcsw chip select to write. defines the delay from the assertion of chip select until the write strobe and byte enables are asserted. see table 3-7 on page 56 for the ac tual number of clock cycles. r/w 0xf 9:6 tpm this field determines the number of cycles required from a burst address change until read data is vali d if the pm bit is set in the mem_stcfg n register. see table 3-7 on page 56 for the ac tual number of clock cycles. ta determines the access time for the first beat of each burst. r/w 0xf 5:0 ta the ta parameter determines the number of cycles required for the assertion of the chip select. for page mode accesses ta determines the access time up to the first beat of each burst, or the first beat after a page mode wrap. see table 3-7 on page 56 for the ac tual number of clock cycles. r/w 0x3f, except for mem_sttime0 where the default value is 0x1d.
58 amd alchemy? au1000? processor data book - preliminary static bus controller 30360d mem_sttime0 (lcd, pcmcia config) offset = 0x1004 bit31302928272625242322212019181716151413121110 9 8 7 6 5 4 3 2 1 0 tmst tmsu tmih tist tisu def.11111111111111111111111111011101 mem_sttime1 (lcd, pcmcia config) mem_sttime2 (lcd, pcmcia config) mem_sttime3 (lcd, pcmcia config) offset = 0x1014 offset = 0x1024 offset = 0x1034 bit31302928272625242322212019181716151413121110 9 8 7 6 5 4 3 2 1 0 tmst tmsu tmih tist tisu def.11111111111111111111111111111111 bits name description r/w default 31:24 tmst this field specifies the str obe width during memory accesses to pcmcia or lcd chip selects. the timing duration depends on the time-scale option mem_stcfg n [ts]: when ts=0, (tmst + 2) is the number of cycles to the end of the strobe; however, the read occurs at (tmst + 1). when ts=1, [(4 * tmst) + 2] is the number of cycles to the end of the strobe; however, the read occurs at [(4 * tmst) + 1]. r/w 0xff 23:17 tmsu this field specifies the setup time from chip select to strobe dur- ing memory accesses to pcmcia or lcd chip selects. see table 3-7 on page 56 for the ac tual number of clock cycles. r/w 0x7f 16:11 tmih this field specifies the hold time for address, data, and chip selects from the end of the strobe for both memory and i/o cycles to pcmcia or lcd chip selects. see table 3-7 on page 56 for the ac tual number of clock cycles. r/w 0x3f 10:5 tist this field specifies the strobe width for i/o accesses for a chip select configured for pcmcia. this is a don?t care for lcd timing diagram. the timing duration depends on the time-scale option mem_stcfg n [ts]: when ts=0, (tmst + 2) is the number of cycles to the end of the strobe; however, the read occurs at (tmst + 1). when ts=1, [(4 * tmst) + 2] is the number of cycles to the end of the strobe; however, the read occurs at [(4 * tmst) + 1]. r/w 0x3f, except for mem_sttime0 where the default value is 0x3e. 4:0 tisu this field specifies the setup ti me from chip select to strobe dur- ing i/o accesses for pcmcia. this is a don?t care for lcd timing diagram. see table 3-7 on page 56 for the ac tual number of clock cycles. r/w 0x1f, except for mem_sttime0 where the default value is 0x1d.
amd alchemy? au1000? processor data book - preliminary 59 static bus controller 30360d 3.2.1.3 static chip select address configuration registers (mem_staddr n ) the static memory chip-select ad dress configuration registers ( mem_staddr n ) assign an address range for each chip select. as shown below, each register contains a base address, an address comparison mask, and an enable bit. once enabled, a chip select is asserted when the following condition is met: (phys_addr & addr_mask) == base_addr where: phys_addr: 36-bit physical address output on the internal system bus (from the tlb for memory-mapped regions) addr_mask: address comparison mask taken from csmask base_addr: chip select base address taken from csba note that chip select regions must be programmed so that ea ch chip select occupies a unique area of the physical address space. programming overlapping chip select regions results in undefined operation. mem_staddr0 - rcs0# address configuration offset = 0x1008 bit31302928272625242322212019181716151413121110 9 8 7 6 5 4 3 2 1 0 e csba csmask def.000rs0001111111000011111111111111 mem_staddr1 - rcs1# address configuration mem_staddr2 - rcs2# address configuration mem_staddr3 - rcs3# address configuration offset = 0x1018 offset = 0x1028 offset = 0x1038 bit31302928272625242322212019181716151413121110 9 8 7 6 5 4 3 2 1 0 e csba csmask def.00001111111111111111111111111111 bits name description r/w default 31:29 ? reserved. should be cleared. r 0 28 e enable. 0 chip select is disabled. 1 chip select is enabled. r/w 0, except for mem_staddr0 (note 1) note 1. the enable (e) bits for chip selects rcs1#, rcs2#, and rcs 3# are automatically cleared (dis abled) coming out of a runtim e or hardware reset. for rcs0#, however, the reset value of the e bit depends on romsel: holding romsel low indicates that rom should be used for the boot vector (and rcs0#?s e bit is set) ; otherwise, rcs0# is disabled . see also section 8.3 "boot" on page 198. 27:14 csba chip select base address. specifies bits 31:18 of the phys ical base address for this chip select. the upper nibble of the chip select address is determined by the device type selected in mem_stcfg n [dty]. the lower bits of the base address are zeros. r/w 0x3fff, except for mem_staddr0 where the default value is 0x7f0. 13:0 csmask chip select address mask. specifies bits 31:18 of the address comparison mask used to decode this chip select. (the upper nibble of the address com- parison mask is determined by mem_stcfg n [dty]. the lower bits of the mask are zeros.) r/w 0x3fff
60 amd alchemy? au1000? processor data book - preliminary static bus controller 30360d 3.2.2 static ram, i/o device and flash device types this section describes the static ram interfac e which is implemented when the device type ( mem_stcfg n [dty]) is pro- grammed to 0, 1 or 3. (see se ction 3.2.1.1 "static bus configuration registers" on page 54.) the static ram, i/o device and flash device types are all simi lar. the i/o device type is identical to the static ram type except that it expects the upper nibble of the system address (bits 35:32) to be 0xd. the only difference betw een the flash device type and the static ram device type is that the flash timing allows for a ch ip select hold time after a write pulse using mem_sttime n [twcs]. other than these differences, the static ra m, i/o device and flash device types share the same timing and control signals. the control signals are shown in table 3-9. 3.2.2.1 static memory timing the following figures show static memory timing. figure 3-4 on page 61 illustrates static me mory read timing, and figure 3- 6 on page 62 illustrates static memory write timing. the ew ait# timing diagrams are presented to show how ewait# will hold the cycle past ta for reads and twp for writes. setup, hold, and delay timing specifications (electrical switch ing characteristics) are presented in section 11.0 "electrical and thermal specifications" on page 234. (see section 11.4.2 "static bus controller timing" on page 240.) timing parameters do not take into a ccount system bus overhead which may add inter-access delays. these delays are dependent on system design and are affected by the number of bus masters and the ability of other devices to hold the bus. table 3-9. static ram, i/o device and flash control signals signal input/ output description rad[31:0] o address bus rd[31:0] io data bus rben[3:0]# o byte enables: rben0# corresponds to rd[7:0]. rben1# is for rd[15:8]. rben2# is for rd[23:16]. rben3# is for rd[31:24]. rwe# o write enable roe# o output enable rcs[3:0]# o programmable chip selects (4 banks). rcsn# is not used when configured as a pcmcia device. ewait# i can be used to stretch the bus access time when enabled through mem_stcfg n [ew].
amd alchemy? au1000? processor data book - preliminary 61 static bus controller 30360d read timing read accesses to the static bus always retr ieve 32-bits of data. as such, all four byte enables are asserted during the 32- bit access or the two 16-bit beats. the control signals (r csn#, roe#, and rben[1:0]#) span both accesses. the only sig- nal that changes state to indicate the start of the second beat is raddr[1]. figure 3-4. static memory read timing (single read followed by burst) figure 3-5. static memory read ewait# timing addr1 addr2 addr2+4 addr2+8 addr2+12 data1 data2a data2b data2c data2d tpm ta tcsh ta rcs n# rben[3:0]# rwe# roe# rad[31:0] rd[31:0] tpm tpm tcs_oe burstsize[2:0] roe# ewait# ta rcs n#
62 amd alchemy? au1000? processor data book - preliminary static bus controller 30360d write timing the timing diagrams below show the static bus write timing for i/o and sram device types. figure 3-6 shows a single 32- bit write on a 32-bit chip select. figure 3-6. static memory write timing figure 3-7. static memory write ewait# timing addr data tw p tcsw tw c s rcs n# rben[3:0#] rwe# roe# rad[31:0] rd[31:0] tw p rwe# ewait# tw c s rcs n#
amd alchemy? au1000? processor data book - preliminary 63 static bus controller 30360d 3.2.3 pcmcia/compact flash device type because of the similarity of compact flash and pcmcia, refere nces to pcmcia should be taken as applicable to compact flash except where noted. the pcmcia peripheral is designed to the pcmcia2.1 specification?but only for the bus trans- actions as described in this section. the au1000 processor provides a pcmcia host adapter when th e device type is programmed for pcmcia. the static con- troller interface provides the required bus signals necessary to control a pcmcia interface. auxiliary signals, such as card detect and voltage sense, can be implemented with gpios if desired. the pcmcia host interface adapter will support memory, attribute and i/o transactions. external logic can be added to support dma transfers. the au1000 processor supports only 8- and 16-bit load and store in structions (byte and halfword instructions) to pcmcia devices. 32-bit accesses are not supported. the pcmcia interface provides control signals defined for pcmcia devices. if two devices are required then external logic must be added to allow for both cards to share the bus. note that when a chip select is programmed as a pcmcia device that the associated rcsn# is not used. the pcmcia interface occupies a 36-bit address space with the u pper 4 bits equal to 0xf. the tlb is required to generate addresses that will activate a chip sele ct with a device type of ?pcmcia?. i/o, memory and attribute spaces are differentiated by addr[31:30]. table 3-10 shows the mapping. note: each of the pcmcia physical address spaces have a ma ximum size of 64 mbytes. any access beyond the 64-mbyte space will alias back into the defined region. table 3-11 enumerates the signals to support the pcmcia interface. table 3-10. pcmcia memory mapping physical address pcmcia mapping 0xf_0xxx_xxxx i/o 0xf_4xxx_xxxx attribute memory 0xf_8xxx_xxxx memory table 3-11. pcmcia interface signals signal input/ output description rad[31:0] o address bus. rd[15:0] io data bus. preg# o when this signal is asserted card access is limited to attribute memory when a mem- ory access occurs and to i/o ports when an i/o access occurs. pce[2:1]# o card enables. poe# o memory output enable. pwe# o memory write enable. pior# o i/o read cycle indication. piow# o i/o write cycle indication. pwait# i this signal is asserted by the card to delay completion of a p ending cycle. note that this signal should be tied high through a resistor when the pcmcia interface is not used. pios16# i 16-bit port select. note that this signal should be tied high through a resistor when the pcmcia interface is not used.
64 amd alchemy? au1000? processor data book - preliminary static bus controller 30360d figure 3-8 and figure 3-9 on page 65 show a one and two card pcmcia implementation. for the two card implementation rad26 is used as a card select signal. both figures assume that the pcmcia card can be hot swapped at any time?note the use of isolation buffers on th e shared bus. if the card is fixed in the syst em much of the interfac e logic can be removed. a compact flash implementation is very similar to the pcmc ia implementation except th at the number of address lines used is fewer. figure 3-8. one card pcmcia interface roe# o output enable. this output enable is intended to be used as a data transceiver con- trol. during a pcmcia transaction, roe# remains asserted (low) as configured in the timing registers ( mem_sttime n ) for reads and negated (high) for writes. table 3-11. pcmcia interface signals (continued) signal input/ output description rd[15:0] roe# pce[2:1]# rad[25:0] preg# poe# pwe# pior# piow# pios16# pwait# gpio[w] gpio[y] deto# deto# buffer oe# pce1# pce2# oe# ce[2:1]# addr[25:0] reg# oe# we# ior# iow# iois16# wait# rdy/bsy# cd1# cd2# 16-bit transceiver with bus hold dir pcmcia socket 0 au1xxx pcmcia host adapter (if an extra gpio is available, this gate can be eliminated.)
amd alchemy? au1000? processor data book - preliminary 65 static bus controller 30360d figure 3-9. two card pcmcia interface rd[15:0] roe# pce1# rad[25:0] preg# poe# pwe# pior# piow# pios16 pwait# gpio[w] gpio[y] deto# deto# buffer oe# s0ce1# s0ce2# oe# ce1# addr[25:0] reg# oe# we# ior# iow# iois16# wait rdy/bsy# cd1# cd2# 16-bit transceiver with bus hold dir pcmcia socket 0 au1 oe# 16-bit transceiver with bus hold dir ce1# addr[25:0] reg# oe# we# ior# iow# wait# ce2# cd1# cd2# pcmcia socket 1 s1ce1# s1ce2# 32 bit gpio[x] gpio[z] deto# ce2# deto# buffer oe# 32 bit pce2# rad26 rad26 0 1 s0ce1# s0ce2# s1ce1# s1ce2# pcmcia host adapter iois16# rdy/bsy#
66 amd alchemy? au1000? processor data book - preliminary static bus controller 30360d 3.2.3.1 pcmcia/compactflash interface the figures on the following pages illustrate the functional timing of the pcmcia interface, including memory read timing, memory write timing, i/o read timing, and i/o write timing. the pwait# timing diagrams are presented to show how pwait# will hold the cycle past tmst for memory reads and writes and tist for i/o reads and writes. setup and hold time requirements are presented in se ction 11.4.2 "static bus controller timing" on page 240. figure 3-10. pcmcia memory read timing figure 3-11. pcmcia memory read pwait# timing read data tmst tmsu tmih pce[2:1]# preg# poe# pwe# pior# piow# pios16# pwait# rad[31:0] rd[15:0] roe# tmih tmst poe# pwait# tmih pce[2:1]#
amd alchemy? au1000? processor data book - preliminary 67 static bus controller 30360d figure 3-12. pcmcia memory write timing figure 3-13. pcmcia memo ry write pwait# timing figure 3-14. pcmcia i/o read timing write data tmst tmsu tmih pce[2:1]# preg# poe# pwe# pior# piow# pios16# pwait# rad[31:0] rd[15:0] tmst pwe# pwait# tmih pce[2:1]# tist tisu tmih read data pce[2:1]# preg# poe# pwe# pior# piow# pios16# pwait# rad[31:0] rd[15:0]
68 amd alchemy? au1000? processor data book - preliminary static bus controller 30360d figure 3-15. pcmcia i/o read pwait# timing figure 3-16. pcmcia i/o write timing figure 3-17. pcmcia i /o write pwait# timing tist pior# pwait# tmih pce[2:1]# write data tist tisu tmih pce[2:1]# preg# poe# pwe# pior# piow# pios16# pwait# rad[31:0] rd[15:0] tist piow# pwait# tmih pce[2:1]#
amd alchemy? au1000? processor data book - preliminary 69 static bus controller 30360d 3.2.4 lcd controller device type the au1000 processor provides a lcd controller host adapter when the device type is programmed for an lcd. the static controller interface provides the bus signals ne cessary to interface to most lcd controllers. a dedicated clock lclk is provided for the lcd interface. the lclk rate is the system bus rate divided by a factor pro- grammed in mem_stcfg0 [d5]; see section 3.2 "static bus controller" on page 53. the au1000 supports only 8- and 16-bit load and store instruct ions (byte and halfword instructions) to the lcd controller interface; 32-bit accesses are not supported. the lcd controller occupies 36 bit address space with the upper 4 bits equal to 0xe. the mmu is required to generate addresses that will generate a chip select with a device type of ?lcd?. table 3-12 lists the control signal s to support the lcd controller. table 3-12. lcd controller interface signals signal input/output description rad[31:0] o address bus rd[15:0] io data bus rcs[3:0]# o chip selects lclk o interface clock lwait# i extend cycle lrd[1:0]# o read indicators lwr[1:0]# o write indicators
70 amd alchemy? au1000? processor data book - preliminary static bus controller 30360d 3.2.4.1 lcd controll er interface timing the following figures shows the lcd timing. the lwait# timi ng diagrams are presented to show how lwait# will hold the cycle past tmst for memory reads and writes and tist for i/o reads and writes. lwait# timing requirements as well as setup and hold times ar e presented in section 11.4.2 "static bus controller timing" on page 240. figure 3-18. lcd controller timing figure 3-19. lcd read lwait# timing figure 3-20. lcd write lwait# timing input output lclk rad[31:0] rcs n# lrd[1:0]# lwr[1:0#] rd[15:0] tcsh ta tcsw tw c h tw p ta lrd[1:0#] lwait# rcs n# tw p lwr[1:0] lwait# tw c s rcs n#
amd alchemy? au1000? processor data book - preliminary 71 static bus controller 30360d 3.2.5 static bus controller programming considerations 3.2.5.1 page mode transfers the static bus controller provides a page mode for quick read access to sequential locations in memory. setting mem_stcfg n [pm] selects page mode operation for the chip select. th e burst size (4 or 8 beats) for page mode transfers is programmed in mem_stcfg n [bs]. depending on the speed of the external memory device , the system designer can adjust two timing parameters in mem_sttime n for page mode transfers: ta is the time from chip select assertion to the first beat of valid data. ta is the time required for the initial access to a peripheral device. ta must allow time for the peripheral device to load its read buffer or activate the next page. note that the page size depends on the peripheral device. tpm is the time between beats. figure 3-4 "static memory read timing (single read followed by burst)" on page 61 shows an example page mode read with the timing parameters ta and tpm. the static bus controller does not check for page boundarie s during page mode reads. the addressing is sequential regardless of alignment. an access which crosses a page boundary may return invalid data if tpm does not allow enough time for the external memory device to update its read buffer or activate the next page. if the system designer cannot ensure adequate address alignment to avoid crossing page b oundaries, tpm must be long enough to accommodate poten- tial page updates. in general, page-boundary timing issues do not arise for instruction fetches because they are always accessed first-word- first and therefore are properly aligned. data fetches, howeve r, may have page-boundary timing issues because they are accessed critical-word-first. note that ewait# can delay only the start of the burst (exten d the ta timing). that is, ewait# cannot be used to account for varying timing between beats (extend the tpm timing) that may occur even for transfers within a page. halfword ordering and 16-bit chip selects because the static bus controller is no t aware of the endian mode of the au1 core, potential halfword swapping conflicts can arise. upon reset, chip selects default to little-endian byte ordering ( mem_stcfg [be] = 0). figure 3- 21 shows the data formats for the 32-bit system bus and for a little-endi an 16-bit chip select. figure 3-21. 16-bit chip select little-endian data format (default) when a 16-bit chip select is in little- endian mode, the static bus controller acce sses the least-significant halfword cd at physical offset 0 and accesses the most-significant halfword ab at physical offset 2. when the au1 core is also in little- endian mode, the requested au1 co re offsets match the physical offsets of the 16 -bit device. that is, the static bus control- ler and the au1 core have the same view of memory. however, when the processor core is in big-endian mode, the default ordering of the static bus cont roller effectively reverses the ordering of the halfwords from what the big-endian au1 core expects, as shown in figure 3-22. a d bc c d a b 32-bit system bus format 16-bit static bus little-endian format physical offset 0 physical offset 2 ab little endian offset 0 big endian offset cd 2 31 24 23 16 15 8 7 0 20 15 8 7 0
72 amd alchemy? au1000? processor data book - preliminary static bus controller 30360d figure 3-22. big-endian au1 core and little-endian 16-bit chip select for ram memories, the halfword swapping has no side-effect s because reads and writes are consistent. however, for rom, flash memories, and peripherals, be aware of the following side effects: for rom and flash, the memory contents are halfword- swapped throughout the entire 16-bit device memory. for flash and peripherals, the programming re gister offsets are also halfword-swapped. to prevent halfword swapping, configure th e chip select for big-endian mode ( mem_stcfg [be] = 1) before accessing the memory. (if booting from static memory , see section 8.3.1 "endianness and 16- bit static bus boot" on page 198.) the static bus controller inverts rad1 for transfers on 16-bit chip selects in big-endian mode, as shown in figure 3-23. figure 3-23. big-endian au1 core and big-endian 16-bit chip select processor big-endian off set device physical offset a b2 0 6 4 10 8 0 2 4 6 8 10 c d a b c d a b c d ab little endian offset 0 big endian offset cd 2 15 8 7 0 20 a d bc 32-bit system bus format 31 24 23 16 15 8 7 0 processor big-endian offset device physical offset a b0 2 4 6 8 10 0 2 4 6 8 10 c d a b c d a b c d ab little endian offset 0 big endian offset cd 2 a d bc 32-bit system bus format 31 24 23 16 15 8 7 0 15 8 7 0 20
amd alchemy? au1000? processor data book - preliminary 73 4 dma controller 30360d 4.0 dma controller the au1000 processor contains an eight-channel dma controller . each channel is capable of transferring data between memory and any of the integrated peripherals or between memory and a memory-mapped fifo through the static control- ler using a gpio as a request. note that memory-to-memory transfers are not supported by t he dma controller. that is, one side of the dma transfer must have an incrementing address (memory buffer), while the other side must have a fixed address (fifo). gpio[4] and gpio[5] can be programmed to act as external dm a request signals. when configured for this special system function, the pins are labeled as follows: gpio[4] becomes dma_req0. gpio[5] becomes dma_req1. see section 4.2, "using gpio as external dma requests (dma _reqn)" to configure these gp io signals to act as dma requests. 4.1 dma configuration registers each channel of the dma is configured by a register block. a channel register block contains seven registers. the 36-bit physical base address of the register block for each channel is shown in table 4-1. table 4-1. dma channel base addresses dma channel physical base address kseg1 base address priority dma0 0x0_1400_2000 0x_b400_2000 0 (highest) dma1 0x0_1400_2100 0x_b400_2100 1 dma2 0x0_1400_2200 0x_b400_2200 2 dma3 0x0_1400_2300 0x_b400_2300 3 dma4 0x0_1400_2400 0x_b400_2400 4 dma5 0x0_1400_2500 0x_b400_2500 5 dma6 0x0_1400_2600 0x_b400_2600 6 dma7 0x0_1400_2700 0x_b400_2700 7 (lowest)
74 amd alchemy? au1000? processor data book - preliminary dma controller 30360d each register block contains the registers shown in table 4-2. table 4-3 shows the different peripherals that are capable of dma. the device id, transfer size, and transfer width (device fifo width) are config urable fields in the dma_mode register. the fifo address is a physical address whose address should be programmed in the dma_peraddr register and in the dah field of the dma_mode register. enabling multiple dma channels with the same device id is undefined. table 4-2. dma channel configuration registers offset register name description 0x0000 dma_moderead read channel mode register 0x0000 dma_modeset set bits in channel mode register 0x0004 dma_modeclr clear bits in channel mode register 0x0008 dma_peraddr address of peripheral fifo 0x000c dma_buf0addr starting address of buffer 0 0x0010 dma_buf0size transfer size and remaining transfer count for buffer 0 0x0014 dma_buf1addr starting address of buffer 1 0x0018 dma_buf1size transfer size and remaining transfer count for buffer 1 table 4-3. peripheral addresses and selectors peripheral device device id transfer size device fifo width fifo physical address uart 0 transmit 0 programmable 8 0x0_1110_0004 uart 0 receive 1 programmable 8 0x0_1110_0000 dma_req0 (gpio[4]) 2 programma ble programmable programmable dma_req1 (gpio[5]) 3 programma ble programmable programmable ac97 transmit 4 4 16 0x0_1000_0008 ac97 receive 5 4 16 0x0_1000_0008 uart3 transmit 6 programmable 8 0x0_1140_0004 uart3 receive 7 programmable 8 0x0_1140_0000 usb device endpoint 0 receive 8 4 8 0x0_1020_0000 usb device endpoint 0 transmit 9 4 8 0x0_1020_0004 usb device endpoint 1 transmit 10 4 8 0x0_1020_0008 usb device endpoint 2 transmit 11 4 8 0x0_1020_000c usb device endpoint 3 receive 12 4 8 0x0_1020_0010 usb device endpoint 4 receive 13 4 8 0x0_1020_0014 i 2 s transmit 14 4 programmable 0x0_1100_000 i 2 s receive 15 4 programmable 0x0_1100_0000
amd alchemy? au1000? processor data book - preliminary 75 dma controller 30360d 4.1.1 dma channel mode registers each dma channel is controlled by a mode register. the current value of the register can be read from the dma_moderead register but can not be set to an arbitrary value in a single operation. instead, th e configuration register is controlled by two registers: dma_modeset and dma_modeclr . the dma_modeset register sets bits in the channel mode register when the corresponding bit is written as a one. (bits written as zero do not affect the corresponding mode bit.) the dma_modeclr register clears bits in the channel mode register when the corresponding bit is written as a one. (bits written as zero do not affect the corresponding mode bit.) the au1000 processor has been designed to simplify the dma control process by removing the need for a semaphore to control access to the registers. this is bec ause there is no need to read, modify, write, as there are separate registers for setting and clearing a bit. in this way a function can free ly manipulate the dma channels associated with that function. an arbitrary value may be written to a field within the register with the following sequence: dma_modeset = new_value & field_mask; dma_modeclr = ~new_value & field_mask; the transfer size and device width fields must be programm ed to match the fifo of the peripheral chosen with the did field according to table 4-3. for the uart fifos the transfer size is programmable. it is the programmers responsibility to insure that the transfer size matches the trigger depth set in the uart fifo control re gister. see section 6.7 "uart interfaces" on page 151 for more information. for the i 2 s fifos the transfer width is programmable. it is the prog rammers responsibility to insure that the transfer width field matches the word size in the i 2 s configuration register and that memory is packed accordingly. see section 6.6 "i2s controller" on page 146 for more information. for external dma using gpio signals as requests (dma_req n ), the system designer must en sure that the transfer size and device width match the external fifo and that memory is packed accordingly. note that before issuing a dma request, the receiving or trans mitting fifo must be prepared to complete a full transaction (4 or 8 datums, depending on dma_mode [ts]) without risking overflow or underflow. dma_moderead - read dma mode register offset = 0x0000 dma_modeset - set dma mode register offset = 0x0000 dma_modeclr - clear dma mode register offset = 0x0004 bit31302928272625242322212019181716151413121110 9 8 7 6 5 4 3 2 1 0 dah did be dr ts dw nc ie h g ab d1 be1 d0 be0 def.00000000000000000000000000000000 bits name description r/w default 31:24 ? reserved. should be cleared. r 0 23:20 dah device address high. provides the most significant 4 bits of physical device address. r/w 0 19:16 did device id. identifies the peripheral de vice to act as source or destination; see table 4-3. r/w 0 15:14 ? reserved. should be cleared. r 0 13 be big endian. 0 little endian byte order 1 big endian byte order r/w 0 12 dr device read. 0 data is transferred from memory to device. 1 data is transferred from device to memory. r/w 0 11 ts transfer size. number of datums tr ansferred per transaction. the device width is programmed in dw. 0 4 datums. (valid for all device widths.) 1 8 datums. (valid for 8-bit and 16-bit device widths only.) r/w 0
76 amd alchemy? au1000? processor data book - preliminary dma controller 30360d 10:9 dw device fifo width. 00 transfer width is 8 bits. 01 transfer width is 16 bits. 10 transfer width is 32 bits. (not valid for ts=1.) 11 reserved rw 0 8 nc not coherent. 0 memory reads and writes are marked coherent on the system bus. 1 memory reads and writes are marked non coherent on the system bus. for more information on coherency see section 2.8.2 "sbus coherency model" on page 41 for more information on coherency. r/w 0 7 ie interrupt enable. 0 no interrupts will be generated. 1 interrupts are generated when either d1 or d0 is set. r/w 0 6 h channel halted. 0 channel is active. 1 channel is halted. this bit should be used to determine if the channel has been halted after the g bit has been cleared. r0 5 g channel go. setting the channel go bit enables the channel. when this bit is cleared the dma controller does not arbitrate for this channel regardless of the state of the buffer enable bits. when the go bit is cleared by software the channel configuration should not be modified until the dma controller sets the halt bit to indicate that the c hannel is inactive and therefore safe to be reconfigured. r/w 0 4 ab active buffer. 0 buffer 0 is currently in use by the dma. 1 buffer 1 is currently in use by the dma. this field can be read to determine what buffer the dma will service next if there is not a dma transaction in progress. during a dma transaction this bit will reflect the buffer currently being used. note that the dma alternates between the two buffers. in other words, it is not possible to only use one buffer, dma transactions must be switched between each buffer. r0 3 d1 done 1. the d1 bit is set by the dma controller to indicate that a transfer to or from buffer 1 is complete. th is bit must be cleared by the processor. r/w 0 2 be1 the be1 bit enables buffer 1. this bit is set by the processor and cleared by the dma controller when the buffer has been filled or emptied. this bit may be cleared by the processor only when the h bit is set. r/w 0 1 d0 done 0. the d0 bit is set by the dma controller to indicate that a transfer to or from buffer 0 is complete. th is bit must be cleared by the processor. r/w 0 0 be0 the be0 bit enables buffer 0. this bit is set by the processor and cleared by the dma controller when the buffer has been filled or emptied. this bit may be cleared by the processor only when the h bit is set. r/w 0 bits name description r/w default
amd alchemy? au1000? processor data book - preliminary 77 dma controller 30360d 4.1.2 dma peripheral device address the peripheral device address register contains a pointer to the peripheral fifo to be used as a source or destination. software is responsible for matching the peripheral address to the correct value of the device id (did) field in the mode register. the correspondence betw een fifo address and did values is shown in table 4-3. the physical address of the fifo must be used. the dah field from the dma_mode register is used as the most significant four bits of the fifo physical address. 4.1.3 dma buffer starting address registers each dma channel has two buffers, labeled buffer0 and buffer1. the starting address of each buffer should be written to the dma_buf0addr and dma_buf0addr registers respectively. the starting address must be cache line (32 bytes) aligned. the 4 most significant bits of the buffer address are held in the bah field of the dma_buf0size and dma_buf1size regis- ters. the starting address must explicitly be written before each dm a transaction, even if the address has not changed from the previous, as dma_bufnaddr will change during the dma transaction. note that the dma alternates between the two buffers. in other words, it is not possible to use only one buffer?dma trans- actions must be switched between each buffer. the ab bit in the dma_mode register can be used to determine the active buffer. dma_peraddr - dma peripheral address register offset = 0x0008 bit31302928272625242322212019181716151413121110 9 8 7 6 5 4 3 2 1 0 addr def.00000000000000000000000000000000 bits name description r/w default 31:0 addr peripheral fifo address. r/w 0 dma_buf0addr - buffer0 starting address dma_buf1addr - buffer1 starting address offset = 0x000c offset = 0x0014 bit31302928272625242322212019181716151413121110 9 8 7 6 5 4 3 2 1 0 addr def.00000000000000000000000000000000 bits name description r/w default 31:0 addr lower 32 bits of the physical starting address of the dma memory buffer. r/w 0
78 amd alchemy? au1000? processor data book - preliminary dma controller 30360d 4.1.4 dma channel buffer size registers the size of each dma buffer is given by the dma_buf0size and dma_buf1size registers. the buffer size registers also contributes the most significant four bits of the buffer physical address. this register should be programmed with the block size of th e buffer in datums. while a dma transaction is in progress, it indicates the number of datums remaining in the transfer. note that the dma alternates between the two buffers. in other words, it is not possible to only use one buffer, dma trans- actions must be switched between each buffer. the active-buffer bit dma_mode [ab] can be used to determine which buffer is active at a given time. 4.2 using gpio as external dma requests (dma_req n ) to use gpio[4] or gpio[5] as an external dma request (dma_req n ) follow these steps: 1) write the sys_pininputen to enable the gpio to be used as an input. see section 7.3 "general purpose i/o and pin functionality" on page 183 for more information. 2) tri-state the gpio to make it an input through the sys_triout register. see section 7.3 "general purpose i/o and pin functionality" on page 183 for more information. 3) set the dma_peraddr register to point to the external device data port. the static bus controller must be configured correctly to recognize this address. 4) program the mode register to match the direct ion of transfer and peripheral attributes. the dma_req n signal must be driven high to request a dma transfer and must remain high until the dma transaction is started. once started, the dma transacti on continues until finished regardless of the dma request si gnal state. a dma transaction refers to a dma transfer of one transf er size as defined in the dma mode register ( dma_mode [ts]). dma_req n should be tied to the external fifo th reshold indicator. in this way the dma_req n signal asserts when the fifo threshold is reached and remains asserted until the fifo fills or empties past the thre shold (after the dma transac- tion starts). dma_req n should then negate after the fifo threshold is met from the opposite direction (approaches full for a transmit or approaches empty for a read). the threshold shou ld be designed such that a complete dma transaction (4 or 8 datums) can occur without risking overflow or underflow. dma_buf0size - buffer 0 size dma_buf1size - buffer 1 size offset = 0x0010 offset = 0x0018 bit31302928272625242322212019181716151413121110 9 8 7 6 5 4 3 2 1 0 bah size def.00000000000000000000000000000000 bits name description r/w default 31:20 ? reserved. should be cleared. r/w 0 19:16 bah buffer address high. provides the 4 most significant bits of the buffer address. r/w 0 15:0 size buffer size and count remaining. indicates the number of datums remaining in the current transfer. r/w 0
amd alchemy? au1000? processor data book - preliminary 79 dma controller 30360d 4.3 programming considerations the following pseudo code is for setting up and servicing a dma channel: setupdma() { make sure interrupts are enabled globally (cp0 reg 12, bit 0) enable interrupt controller for this dma channel, high/level program the dma controller { dma_modeclr = 0xffffffff dma_buf0size = buffer size (up to 65535) dma_buf1size = buffer size (up to 65535) dma_peraddr = address of peripheral fifo dma_buf0addr = physical base address of buffer dma_buf1addr = physical base address of next buffer write the dma_modeset register { enable interrupt enable both buffers set endianness set data width, 8-bit, 16-bit, 32-bit set device id set transfer size, 4-datum burst, 8-datum burst set coherency = 0 (memory is coherent) set go = 1 } } interrupthandler() { note: this routine assumes it is called from context save/ restore routine at 0x80000200. check for hardware interrupt from interrupt controller 0, request 0: (cp0 reg 13, bit 10) = 1 read interrupt controller 0 ic_req0int (interrupt status) and check if source is from this dma channel, bits[13:6] if it is this dma channel { check dma_moderead to see which buffer is done: d0 or d1 if (d0 is set) { write dma_modeclr bit d0 = 1 to clear interrupt if there is another buffer to send { dma_buf0addr = physical base address of buffer dma_buf0size = buffer size (up to 65535) write dma_modeset bit be0 = 1 to enable buffer } } } if (d1 is set) { write dma_modeclr bit d1 = 1 to clear interrupt if there is another buffer to send { dma_buf1addr = physical base address of buffer dma_buf1size = buffer size (up to 65535) write dma_modeset bit be1 = 1 to enable buffer } } } } issue sync }
80 amd alchemy? au1000? processor data book - preliminary dma controller 30360d
amd alchemy? au1000? processor data book - preliminary 81 5 interrupt controller 30360d 5.0 interrupt controller there are two interrupt controllers in the au1000 processor. each interrupt controller supports 32 interrupt sources. inter- rupts can generate a signal to bring the au1000 processor ou t of an idle0 or idle1 state and generate a cpu interrupt. each interrupt controller has two outputs referred to as requests 0 and 1. each of these outp uts are connected to the cpu core. see section 2.5 "exceptions" on page 25 for a complete au1000 processor interrupt architecture discussion. table 5- 1 shows the interrupt controller connections to the cpu. 5.1 interrupt controller sources table 5-2 on page 82 shows the mapping of interrupt sources for interrupt controller 0 and 1. as shown, interrupt controller 1 sources are a linear mapping of the 32 gpios. care should be taken to select the correct interrupt type (level or edge triggered) so that an interrupt is not missed. in gen- eral, level interrupts are chosen when multiple sources from a single peripheral might cause an interrupt. in this way the programmer will not miss a subsequent interrupt from a particular source while servicing the previous one. edge triggered interrupts can be used when there is only a sing le source for an interrupt. edge triggered interrupts must be used when an interrupt is caused by an internal event and not tied to a register bit where it is latched and held until cleared by the programmer. details about the interrupt sources can be found in the respective peripheral sections. table 5-1. interrupt controller connections to the cpu interrupt source cp0 cause register bit interrupt controller 0: request 0 request 1 10 11 interrupt controller 1: request 0 request 1 12 13
82 amd alchemy? au1000? processor data book - preliminary interrupt controller 30360d table 5-2. interrupt sources controller interrupt number source type 0 0 uart0 high level 0 1 uart1 high level 0 2 uart2 high level 0 3 uart3 high level 0 4 ssi0 high level 0 5 ssi1 high level 0 6 dma0 high level 0 7 dma1 high level 0 8 dma2 high level 0 9 dma3 high level 0 10 dma4 high level 0 11 dma5 high level 0 12 dma6 high level 0 13 dma7 high level 0 14 toy (tick) rising edge 0 15 toy match 0 rising edge 0 16 toy match 1 rising edge 0 17 toy match 2 rising edge 0 18 rtc (tick) rising edge 0 19 rtc match 0 rising edge 0 20 rtc match 1 rising edge 0 21 rtc match 2 rising edge 0 22 irda transmit high level 0 23 irda receive high level 0 24 usb device interrupt request high level 0 25 usb device suspend interrupt rising/falling edge 0 26 usb host low level 0 27 ac97 acsync rising edge 0 28 mac 0 dma done high level 0 29 mac 1 dma done high level 0 30 reserved n/a 0 31 ac97 command done rising edge 1 n = 0..31 gpio[n] system dependent
amd alchemy? au1000? processor data book - preliminary 83 interrupt controller 30360d figure 5-1 shows the interrupt controller logic diagram. where applicable, the names in the diagram correspond to bit n in the relative control register. figure 5-1. interrupt controller logic 5.2 register definitions the design of the software interface to the interrupt controller is based on the premise that software tasks should be able to access the value and control of an individual port without blocking other tasks from accessing ports of interest to them. this interrupt controller design removes the need to arbitrate via a semaphore access to the interrupt controller registers. the result is faster and simpler interrupt controller accessing. table 5-3 shows the base address for each interrupt controller. each interrupt controller has an identical set of registers that controls its set of 32 interrupt s. table 5-4 on page 84 shows the interrupt controller registers and their associated offsets. certain offsets are shared but address different internal regi s- ters depending on whether the access is a read or a write. the register description details the functionality of the register. bit n of a particular register is associated with interrupt n of the corresponding controller. table 5-3. interrupt controller base addresses name physical base address kseg1 base address ic0_base 0x0_1040_0000 0x_b040_0000 ic1_base 0x0_1180_0000 0x_b180_0000 ic_testbit [tb] interrupt ic_src [n] ic_cfg2 [n] ic_cfg1 [n] ic_cfg0 [n] level/edge logic edge detection ic_rising [n] (rising edge detect) ic_falling [n] (falling edge detect) high level low level ic_assign [n] ic_mask [n] ic_req1int [n] cpu request 1 32 total 32 total cpu request 0 ic_req0int [n] 0 1 (source select) decision number n source
84 amd alchemy? au1000? processor data book - preliminary interrupt controller 30360d table 5-4. interrupt controller registers offset register name type register description default 0x0040 ic_cfg0rd r configuration 0 register configuration 1 register configuration 2 register the combined field consisting of ic_cfg2 [ n ], ic_cfg1 [ n ], and ic_cfg0 [ n ] specifies the trigger characteristics for interrupt n as shown in table 5-5. unpred 0x0040 ic_cfg0set w 0x0044 ic_cfg0clr w 0x0048 ic_cfg1rd r unpred 0x0048 ic_cfg1set w 0x004c ic_cfg1clr w 0x0050 ic_cfg2rd r unpred 0x0050 ic_cfg2set w 0x0054 ic_cfg2clr w 0x0054 ic_req0int r shows active interrupts on request 0. used by host software to determine the source of the interrupt. 0x0000 0000 0x0058 ic_srcrd r selects the source of the interrupt between a test bit and the designated source. 0 the test bit ( ic_testbit [tb]) is used as interrupt source. 1 peripheral interrupt (controller 0) or gpio signal (controller 1) is used for interrupt source. unpred 0x0058 ic_srcset w 0x005c ic_srcclr w 0x005c ic_req1int r shows active interrupts on request 1. used by host software to determine the source of the interrupt. 0x0000 0000 0x0060 ic_assignrd r assigns the interrupt to one of the cpu requests. 0 assign interrupt to request 1. 1 assign interrupt to request 0. unpred 0x0060 ic_assignset w 0x0064 ic_assignclr w 0x0068 ic_wakerd r controls whether the interrupt can cause a wakeup from idle0 or idle1. 0 no wakeup from idle 1 interrupt will cause wakeup from idle. the associated interrupt must still be enabled to wake from idle. 0x0000 0000 0x0068 ic_wakeset w 0x006c ic_wakeclr w 0x0070 ic_maskrd r interrupt enable. 0 disable the interrupt. 1 enable the interrupt. 0x0000 0000 0x0070 ic_maskset w 0x0074 ic_maskclr w 0x0078 ic_risingrd r designates active rising edge interrupts. if an interrupt is generated off of a rising edge, the associated rising edge detection bit must be cleared after detection. unpred 0x0078 ic_risingclr w 0x007c ic_fallingrd r designates active falli ng edge interrupts. if an interrupt is generated off of a falling edge, the associated falling edge detection bit must be cleared after detection. unpred 0x007c ic_fallingclr w 0x0080 ic_testbit r/w this is a single bit register that is mapped to all the source select inputs for testing purposes. unpred
amd alchemy? au1000? processor data book - preliminary 85 interrupt controller 30360d 5.2.1 interrupt controller registers each register (except the test-bit register) is 32 bits wide with bit n in each register affecting interrupt n in the corresponding controller. the test-bit register contains the test bit which can be used as a test source for each interrupt. figure 5-1 on page 83 shows how the test bit connects to the interrupt source-select logic. certain interrupt controller registers have t he same offset but offer different functiona lity. this is by design. care should b e taken when programming the registers beca use a read from one location may reference something different from a write to the same location. registers ending in *rd, *set and *clr have the following functionality: *rd registers are read only registers will read back the current value of the register. *set registers are write only registers and will set to 1 all bi ts that are written 1. writing a value of 0 will have no impact on the corresponding bit. *clr registers are write only registers and will clear to zero all bits that are written 1. writing a value of 0 will have no impact on the corresponding bit. the three configuration registers have a special func tionality in that the va lue associated with ic_cfg2[ n ], ic_cfg1[ n ], ic_cfg0[ n ] uniquely control interrupt n ?s functionality as shown in table 5-5 on page 86. *rd *set *clr bit31302928272625242322212019181716151413121110 9 8 7 6 5 4 3 2 1 0 func[31:0] def.xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx bits name description r/w default 31:0 func[n] the function of each register is given in table 5-4. func[n] con- trols the functionality of interrupt n in the corresponding control- ler. *rd - read only *set - write only *clr - write only see the following explanation. see table 5-4. ic_testbit offset = 0x0080 bit31302928272625242322212019181716151413121110 9 8 7 6 5 4 3 2 1 0 tb def.xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx bits name description r/w default 31:1 ? reserved. should be cleared. r/w unpred 0 tb test bit value used as an alte rnate interrupt source. r/w unpred
86 amd alchemy? au1000? processor data book - preliminary interrupt controller 30360d 5.3 hardware considerations when using a gpio or peripheral as an interrupt source, it is important that the associated pin functionality has been enabled in the sys_pinfunc register. in addition when using a gpio, the gpio must first be enabled as an input. see sec- tion 7.3 "general purpose i/o and pin functionality" on page 183 for more information. 5.4 programming considerations the au1000 has been designed to simplify the interrupt contro l process by removing the need for a semaphore to control access to the registers. this is because there is no need to r ead, modify, write, as there are separate registers for setting and clearing a bit. in this way a function can freely manipulate the interrupts associated with that function. if using edge triggered interrupts, it is important to clear the associated edge dete ction bit or future interrupts will not be seen. programming an interrupt controller can be broken into the following steps (the set , clr , and rd portion of the register name has been omitted): 1) identify the interrupt number, n, with the associated peripheral or gpio. 2) use ic_src [ n ] to assign the interrupt to the associated peripheral/gp io (or the test bit can be used if testing the inter- rupt). 3) set the ic_cfg2 [ n ], ic_cfg1 [ n ] and ic_cfg0 [ n ] bits to the correct configuration for the corresponding interrupt (edge, level, polarity). 4) assign the interrupt to a cpu request using ic_assign [ n ]. 5) use ic_wake [ n ] to assign the interrupt to wake the processor from idle if necessary or clear this register bit to keep the interrupt from waking the processor from idle. 6) if the interrupt is an edge triggered interrupt, clear the edge detect register ( ic_risingclr or ic_fallingclr ) before enabling. 7) finally, enable the interrupt through ic_mask [ n ]. when taking an interrupt the following steps should be taken: 1) read ic_req0int and ic_req1int to determine the interrupt number n . 2) use ic_fallingrd and ic_risingrd to determine if the interrupt was edge trigger ed. if the interrupt is edge triggered, use ic_fallingclr [ n ] or ic_risingclr [ n ] to clear the edge detection circuitry. 3) if the interrupt is to be disabled write ic_maskclr [ n ] . 4) service the interrupt. table 5-5. interrupt configuration register function ic_cfg2[n] ic_cfg1[n] ic_cfg0[n] function 0 0 0 interrupts disabled 0 0 1 rising edge enabled 0 1 0 falling edge enabled 0 1 1 rising and falling edge enabled 1 0 0 interrupts disabled 1 0 1 high level enabled 1 1 0 low level enabled 1 1 1 both levels and both edges enabled
amd alchemy? au1000? processor data book - preliminary 87 interrupt controller 30360d
amd alchemy? au1000? processor data book - preliminary 88 6 peripheral devices 30360d 6.0 peripheral devices this section provides descriptions of the peripheral devices of the au1000 processor. this includes an ac97 controller, usb host and device interfaces, irda, two 10/100 ethernet macs, i 2 s, four uarts and two synchronous serial interfaces. each peripheral contains an enable register. all other registers within each peripheral?s register block should not be accessed until the enable register is written the correct sequenc e to bring the peripheral out of reset. accessing the periph- eral register block before a peripheral is enabled will result in undefined results. 6.1 ac97 controller the au1000 processor contains an ac97 controller which in corporates an ac-link capable of bridging to an ac97 compli- ant codec. all data being sent and received through the ac97 controller must be 48 khz. 6.1.1 ac97 registers the ac97 controller is controlled by a register block whose physical base address is shown in table 6-1. the register block consists of 5 registers as shown in table 6-2. table 6-1. ac97 base address name physical base address kseg1 base address ac97_base 0x0_1000_0000 0x_b000_0000 table 6-2. ac97 registers offset register name description 0x0000 ac97_config ac-link configuration 0x0004 ac97_status controller status 0x0008 ac97_data tx/rx data 0x000c ac97_cmmd codec command 0x000c ac97_cmmdresp codec command response 0x0010 ac97_enable ac97 block control
amd alchemy? au1000? processor data book - preliminary 89 ac97 controller 30360d 6.1.1.1 ac-link conf iguration register the configuration register contains bits necessa ry to configure and reset the ac-link and codec. 6.1.1.2 ac97 controller status the ac97 controller status register co ntains status bits for the transmit and receive fifos, command status and the codec. ac97_config - ac-link configuration offset = 0x0000 bit31302928272625242322212019181716151413121110 9 8 7 6 5 4 3 2 1 0 rc xs sg sn rs def.00000000000000000000000000000000 bits name description r/w default 31:23 ? reserved. should be cleared. r 0 22:13 rc receive slots. the bits set in rc wi ll control what data from valid slots are put into the input buffer. the corresponding valid bits in the ac 97 tag (slot 0 of sdata_in) must be marked valid for the incoming pcm data to be put in the input buffer. slot 3 is mapped to bit 13, slot 4 to 14 and so on. note: the programmer must ensure that the codec is configured such that there will be valid data in the sl ots corresponding to what receive slots are enabled. r/w 0 12:3 xs transmit slots. the bits making up xmit_slots map to the valid bits in the ac97 tag (slot 0 on sdata_out) and indicate which outgoing slots have valid pcm data. bit 3 maps to slot 3, bit 4 to slot 4 and so on. setting the corresponding bit indicates to the codec that valid data will be in the respective slot. the number of valid bits will designate how many words will be pulled out of the fifo per audio frame. r/w 0 2 sg sync gate. setting this bit to 1 w ill gate the clock from being driven on sync. this allows the sn bit to control the value on sync. in combina- tion with sn, the sg bit can be used to initiate a warm reset. r/w 0 1 sn sync control. this bit controls the value of the sync signal when sg (sync gate) is set. in combination with sg, the sn bit can be used to ini- tiate a warm reset. r/w 0 0 rs ac-link reset (acrst#) control. to initiate a cold ac97 reset, set the rs bit to drive the acrst# signal low. after satisfying the acrst# low time for the codec, clear this bit to negate acrst#. r/w 0 ac97_status - controller status offset = 0x0004 bit31302928272625242322212019181716151413121110 9 8 7 6 5 4 3 2 1 0 xu xo ru ro rd cp te tf re rf def.00000000000000000000000000110010 bits name description r/w default 31:12 ? these bits are reserved. r unpred 11 xu transmit underflow. when set, this bit indicates that the transmit fifo has experienced an underflow. this sticky bit is cleared when written (0 or 1). r0 10 xo transmit overflow. when set, this bit indicates that the transmit fifo has experienced an overflow. this sticky bit is cleared when written (0 or 1). r0 9 ru receive underflow. when set, this bi t indicates that the receive fifo has experienced an underflow. this st icky bit is cleared when written (0 or 1). r0 8 ro receive overflow. when set, this bit indicates that the receive fifo has experienced an overflow. this sticky bit is cleared when written (0 or 1). r0
90 amd alchemy? au1000? processor data book - preliminary ac97 controller 30360d 6.1.1.3 tx/rx data the tx/rx data register is the transmit fifo?s input to the when written to and the receive fifo?s output when read from. each fifo has twelve 16-bit entries. care should be taken to monitor the status register to insure that there is room for data in the fifo for a read or write transa ction. this will be taken care of automat ically if using dma (see section 6.1.3, "programming considerations"). the number of bits set in xmit_slots will correspond with how many samples are pulled out of the fifo and aligned in the respective slots. the number of bi ts set in recv_slots will correspond with the number of samples placed in the fifo from the respective slots in sdata_in. 7 rd ready. this bit is mapped from the codec_ready bit in the sdata_in tag word. it indicates that the codec is properly booted and ready for normal operation. r0 6 cp command pending. this bit indicates that there is a command pend- ing on the ac-link. a write to the codec command register will cause this bit to be set until the command is completed. the com- mand is completed for a write when the data has been written out on slot 2. the command is completed for a read request when the status data has been read from the co rresponding read request. (this means that a read request could be pending for more than 1 cycle depending on the latency of the read.) the command register should not be wr itten until the cp bit is clear. an interrupt can be enabled to indicate when a command is done. the source of this interrupt is an internal pulse so either rising edge or falling edge interrupt should be used for this interrupt. r0 5 ? reserved. r unpred 4 te transmit empty. when set this bit indicates that the transmit fifo is empty. r0 3 tf transmit full. when set this bit i ndicates the transmit fifo is full. r 0 2 ? reserved. r unpred 1 re receive empty. when set this bit indicates that the receive fifo is empty. r0 0 rf receive full. when set this bit indi cates that the receive fifo is full. r 0 ac97_data - tx/rx data offset = 0x0008 bit31302928272625242322212019181716151413121110 9 8 7 6 5 4 3 2 1 0 data_word[15:0] def.00000000000000000000000000000000 bits name description r/w default 31:16 ? reserved. should be cleared. r 0 15:0 data_word data word. this is where data is written to or read from the fifo. each data word is 16 bits. r/w 0 bits name description r/w default
amd alchemy? au1000? processor data book - preliminary 91 ac97 controller 30360d 6.1.1.4 codec command the codec command and command response registers share the same physical address. the codec command register is used to send read and write commands to the codec. for write commands, the data field will be written to the register indicated by the index field. for read commands, the data field should be written zero. the value read from the register indicated by index will appear in the codec response register when the command pending bit in the status register ( ac97_status [cp]) returns to 0. the codec command register should only be written if ac97_status [cp] is 0. 6.1.1.5 codec command response the codec command and response registers share the same physical address. after a read command is sent through the codec command re gister, the response can be read from the codec response register. the command response becomes valid when th e command pending bit in the status register ( ac97_status [cp]) is cleared; however, the response remains valid for only one ac97 frame length in duration (20.8 s). ac97_cmmd - codec command offset = 0x000c bit31302928272625242322212019181716151413121110 9 8 7 6 5 4 3 2 1 0 data rw index def.00000000000000000000000000000000 bits name description r/w default 31:16 data data. these bits will be the actual 16-bit word written to the register indicated by index if rw is a 0. if rw is set (indicating a read), these bits should be written 0. w0 15:8 ? reserved. should be cleared. w 0 7 rw read/write bit (1=read, 0=write). this bit maps to the read/write bit in the command address and designates whether the current opera- tion will be a read or a write. w0 6:0 index codec register index. these bits will address the spec ific register to be read or written to inside the codec. w0 ac97_cmmdresp - codec command response offset = 0x000c bit31302928272625242322212019181716151413121110 9 8 7 6 5 4 3 2 1 0 read_data def.00000000000000000000000000000000 bits name description r/w default 31:16 ? reserved. should be cleared. r 0 15:0 read_data read_data. these bits will be the response to the last read com- mand sent to the codec. the read data becomes valid after the read command is completed ( ac97_status [cp] = 0). note that read_data remains valid for only one ac97 frame (20.8 s) and should therefore be read immediately after ac97_status [cp] is cleared. r0
92 amd alchemy? au1000? processor data book - preliminary ac97 controller 30360d 6.1.1.6 ac97 enable the ac97 enable register is used to enable and reset the enti re ac97 controller block. the routine for bringing the ac97 controller out of reset is as follows: 1) set the ce bit to enable clocks while leaving the block disabled (d=1). 2) clear the d bit to enable the peripheral. 6.1.2 hardware considerations the ac-link consists of the signals listed in table 6-3. for changing pin functionality please refer to the sys_pinfunc register in section 7.3 "general purpose i/o and pin func- tionality" on page 183. ac97_enable - ac97 block control offset = 0x0010 bit31302928272625242322212019181716151413121110 9 8 7 6 5 4 3 2 1 0 dce def.00000000000000000000000000000010 bits name description r/w default 31:2 ? reserved. should be cleared. w 0 1 d ac97 controller disable. setting this bit will reset the ac97 block. after enabling the clock with ce, th is bit should be cleared for normal operation. w1 0 ce clock enable. this bit should be set to enable the clock driving the ac97 controller. it can be cleared to disable the clock for power con- siderations. w0 table 6-3. ac-link signals signal input/ output definition acsync o fixed rate sample sync; muxed with s1dout. acbclk i serial data clock ; muxed with s1din. acdo o tdm output stream; muxed with s1clk. acdi i tdm input stream. acrst# o codec reset; muxed with s1den.
amd alchemy? au1000? processor data book - preliminary 93 ac97 controller 30360d 6.1.3 programming considerations to use the ac97 controller the ac97 bit in the sys_pinfunc [a97] register (see section 7.3 "general purpose i/o and pin functionality" on page 183) must be cleared. th is enables the associated pins for ac97 use. the ac97 block supports dma transfers and interrupts. the us e of the dma or interrupts is program dependent and is not required to use the ac97 controller. to use dma for ac97 memory transfers the transmit and rece ive functions will each need a dedicated dma channel. the dma peripheral address register ( dma_peraddr ) in the dma configuration registers will be set to point to the ac97 ac97_data register. the dma mode register ( dma_mode ) will need to be set up with the correct device id (did). the device read bit (dr) will depend on whether the channel is bei ng used for receive or transmit. typically the device width (dw) should be set to 16 bits and the transfer size bit (ts) should be cleared because the fifo threshold indicators corre- spond to four-datum transfers. this assumes that the au dio samples are aligned in memory on a 16-bit audio sample boundary. the dma will automatic ally monitor the transmit and receive request bits and feed data accordingly. an interrupt (?ac97 command done? in interrupt controller 0) can be enabled to indicate when a command is completed. the source of this interrupt is an internal pulse so either rising edge or falling edge interrupt should be used for this inter - rupt. when the ac97 acsync interrupt is enabled in interrupt controller 0, an interrupt will occur corresponding to the rising edge of the acsync signal. internally a pulse is generated from the rising edge of the acsync signal and fed to the inter- rupt controller. regardless of the edge enabled in the interrup t controller the interrupt will come after the rising edge of acsync. enabling a rising edge interrupt will interrupt the processor closest to the rising edge of acsync. the output fifo for the ac-link is shared for all slots so ca re should be taken that there is a correspondence with the num- ber of valid bits being set and the number of valid samples written to the transmit fifo or aligned in memory for dma or erroneous results will occur. it is the programmer?s responsibili ty to ensure that the number of samples written to the fifo corresponds with the number of valid slots enabled. data will automatically be pull ed out of the fifo in the order of what slots are enabled. in other words if slots 3, 4, 6 and 9 are enabled, the programmer should write samples corresponding to data for slots 3, 4, 6, and 9, in that order, to the fifo. to insure against underflow at least x words should be written per audio frame where x is the number of slots enabled. this is a mean rate over time and the actual write rate may diff er depending on latency requirements, dma buffer size, and the number of slots enabled. care should be taken that there is a correspondence with the number of valid bits that have been set and the number of valid samples read from the receive fifo or erroneous results will occur. the input fifo for the ac-link is shared for all slots so care should be taken that there is a correspondence with the num- ber of valid bits that are set and the num ber of samples read from the receive fifo or erroneous results will occur. it is the programmer?s responsibility to ensure that the number of samp les read from the fifo corresp onds with the number of valid slots enabled. data will automatic ally be put in the fifo in the order of what slots are enabled. in other words if slots 3 and 4, are enabled, the programmer should read samples correspondi ng to data for slots 3 and 4, in that order, from the fifo. to insure against overflow at least x words should be read per audio frame where x is the number of slots enabled. this is a mean rate over time and the actual read rate may differ depending on latency requirements, dma buffer size, and the number of slots enabled.
94 amd alchemy? au1000? processor data book - preliminary usb host controller 30360d 6.2 usb host controller the au1000 processor usb host controller conforms to the open hci in terface specification, revision 1.0, and is usb 1.1 compliant. two root hub ports, port 0 and port 1, are provided. the base of the open hci regi ster block is shown in table 6-4. only 32-bit accesses are allo wed to the open hci registers. all interrupts as described in the open hci specification are supported. these interr upts are combined when brought to the interrupt controller into one active-low interrupt (negative-ed ge triggered does not work). the interrupt controller should be programmed to reflect this by setting th e usb host interrupt to low level. see se ction 5.0 "interrupt controller" on page 81 for details. 6.2.1 usb host enable register this register is not part of the openhci register s; however, it shares the same base address. the usbh_enable register controls the reset and clocks to the usb host controller. wh en initializing the usb host controller the programmer should first enable clocks, then enable the module (remove from reset), then wait for the rd bit to be set before performing open- hci initialization. the correct routine for bringing the usb ho st controller out of reset is as follows: 1) set the ce bit to enable clocks. 2) set the e bit to enable the peripheral (at this time the c and be bits should be configured appropriately for the system). 3) clear the hcfs bit in the hccontrol register to reset the ohci state. 4) wait for the rd bit to be set before issuin g any commands to the openhci controller. to put the usb host controller into rese t the following steps should be taken: 1) set the hcfs bit in the hccontrol register. 2) clear the e and ce bits. table 6-4. usb host base address name physical base address kseg1 base address usbh_base 0x0_1010_0000 0x_b010_0000 usbh_enable offset = 0x7fffc bit31302928272625242322212019181716151413121110 9 8 7 6 5 4 3 2 1 0 rd ce e c be def.00000000000000000000000000000000 bits name description r/w default 31:5 ? reserved. must be cleared. r/w 0 4 rd reset done. wait for this bit to be set before issuing any commands to the openhci controller. note: when writing to the usbh_enable register, this bit position must be 0. r0 3 ce clock enable. when this bit is set, clocks are enabled to the usb host controller. r/w 0 2 e enable. this bit enables the usb host controller. when this bit is clear the controller is held in reset. r/w 0 1 c coherent. if this bit is set memory ac cesses by the controller will be marked coherent on the system bus. when this bit is clear memory accesses by the usb host controller are non coherent. for more information on coherency see section 2.8.2 "sbus coherency model" on page 41 for more information on coherency. r/w 0
amd alchemy? au1000? processor data book - preliminary 95 usb host controller 30360d 6.2.2 usb host signals table 6-5 shows the signals associated with the two usb host ro ot hub ports. the usb root hub port pins have usb 1.1 compliant drivers with the addition of the exter nal circuitry noted in the signal description. for changing pin functionality refer to the sys_pinfunc register in section 7.3 "general purpose i/o and pin functionality" on page 183. 0 be big endian. when this bit is set the c ontroller interprets data buffers in big endian byte order. when this bit is clear the controller interprets data buff- ers in little endian byte order. setting the be bit does not swap the control structures defined in the ohci specification. endpoint des criptors (section 4.2), tr ansfer descriptors (sec- tion 4.3), and the hcca (host controller communications area, section 4.4) should always be written as words to ensure proper operation. r/w 0 table 6-5. usb host signals signal input/output description usbh0p io positive signal of differential usb host port 0 driver. requires an external 15 kohm pull-down resistor and esd protecti on diode (transient voltage suppressor) to be usb 1.1 compliant. termination note: requires an external 20 ohm resistor placed in series within 0.5 inches of the part. muxed with usbdp which controls the pin out of reset. usbh0m io negative signal of differential usb host port 0 driver. requires an external 15 kohm pull-down resistor and esd protecti on diode (transient voltage suppressor) to be usb 1.1 compliant. termination note: requires an external 20 ohm resistor placed in series within 0.5 inches of the part. muxed with usbdm which controls the pin out of reset. usbh1p io positive signal of differential usb host port 1 driver. requires an external 15 kohm pull-down resistor and esd protecti on diode (transient voltage suppressor) to be usb 1.1 compliant. termination note: requires an external 20 ohm resistor placed in series within 0.5 inches of the part. usbh1m io negative signal of differential usb host port 1 driver. requires an external 15 kohm pull-down resistor and esd protecti on diode (transient voltage suppressor) to be usb 1.1 compliant. termination note: requires an external 20 ohm resistor placed in series within 0.5 inches of the part. bits name description r/w default
96 amd alchemy? au1000? processor data book - preliminary usb device controller 30360d 6.3 usb device controller the au1000 processor usb device controller supports endpoints 0, 1, 2, 3, and 4. endpoint 0 is always configured as a bidirectional control endpoint. endpoints 1 and 2 are alwa ys in endpoints and endpoints 3 and 4 are always out end- points. in is from device to host. from the device perspective thes e endpoints are written, so the associated registers are tagged with write or wr. out is from host to device. from the device perspective th ese endpoints are read, so the associated registers are tagged with read or rd. the usb device registers are located off of the base address shown in table 6-6. table 6-7 shows the offsets of each register from the register base. table 6-6. usb device base address name physical base address kseg1 base address usbd_base 0x0_1020_0000 0x_b020_0000 table 6-7. usb device register block name offset description usbd_ep0rd 0x0000 read from endpoint 0 usbd_ep0wr 0x0004 write to endpoint 0 usbd_ep1wr 0x0008 write to endpoint 1 usbd_ep2wr 0x000c write to endpoint 2 usbd_ep3rd 0x0010 read from endpoint 3 usbd_ep4rd 0x0014 read from endpoint 4 usbd_inten 0x0018 interrupt enable register usbd_intstat 0x001c interrupt status register usbd_config 0x0020 write configuration data usbd_ep0cs 0x0024 endpoint 0 control and status usbd_ep1cs 0x0028 endpoint 1 control and status usbd_ep2cs 0x002c endpoint 2 control and status usbd_ep3cs 0x0030 endpoint 3 control and status usbd_ep4cs 0x0034 endpoint 4 control and status usbd_framenum 0x0038 current frame number usbd_ep0rdstat 0x0040 ep0 read fifo status usbd_ep0wrstat 0x0044 ep0 write fifo status usbd_ep1wrstat 0x0048 ep1 write fifo status usbd_ep2wrstat 0x004c ep2 write fifo status usbd_ep3rdstat 0x0050 ep3 read fifo status usbd_ep4rdstat 0x0054 ep4 read fifo status usbd_enable 0x0058 usb device controller enable
amd alchemy? au1000? processor data book - preliminary 97 usb device controller 30360d 6.3.1 endpoint fifo read and write registers the endpoint fifo read and write registers provide access to th e endpoint fifos. each endpoint fifo is unidirectional. fifo read registers may not be written, and fifo wr ite registers return unpredictable results if read. only the least significant byte of the fifo registers contain data 6.3.2 interrupt registers each endpoint has an interrupt enable register and an interrup t status register. the two regi sters have identical formats. when a condition becomes true the corresponding bit is set in the usbd_intstat register. if a bit is set in the interrupt enable register and the corresponding cond ition becomes true, then an interrupt is issued. the interrupt for the usb device should be programmed to high level. interrupts and pending conditions must be cleared by writing a 1 to the corresponding bit in the usbd_intstat register. usbd_ep0rd offset = 0x0000 usbd_ep0wr offset = 0x0004 usbd_ep1wr offset = 0x0008 usbd_ep2wr offset = 0x000c usbd_ep3rd offset = 0x0010 usbd_ep4rd offset = 0x0014 bit31302928272625242322212019181716151413121110 9 8 7 6 5 4 3 2 1 0 data def.00000000000000000000000000000000 bits name description r/w default 31:8 ? reserved. should be cleared. r/w 0 7:0 data data. byte of data to be written to, or read from the endpoint fifo. r/w 0 usbd_inten offset = 0x0018 usbd_intstat offset = 0x001c bit31302928272625242322212019181716151413121110 9 8 7 6 5 4 3 2 1 0 sf h5 h4 h3 h2 h1 h0 c5 c4 c3 c2 c1 c0 def.00000000000000000000000000000000 bits name description r/w default 31:13 ? reserved. should be cleared. r/w 0 12 sf start of frame. this interrupt issues when an sof token is received. r/w 0 11:6 h5:h0 fifo half full. these interrupts issue when the corresponding fifo reaches the half full/half empty mark. the bits correspond as follows: h0 - ep0rd h1 - ep0wr h2 - ep1wr h3 - ep2wr h4 - ep3rd h5 - ep4rd r/w 0
98 amd alchemy? au1000? processor data book - preliminary usb device controller 30360d 6.3.3 device configuration register the device configuration register allows configuration data to be loaded to the controller after reset. the device configuration data is a 25-byt e block which contains the configuration information for the five supported end- points. each endpoint requires five configurat ion bytes in the format shown in figure 6-1. figure 6-1. endpoint configuration data structure 5:0 c5:c0 complete these interrupts issue when a transmission or reception completes on the corresponding fifo. for the read fifo s (ep0rd, ep3rd, and ep4rd) these interrupts indicate the reception of a data0 or data1 packet, or a setup packet (ep0rd fifo only). for the write fifos (ep0wr, ep1wr, and ep2wr) these interrupts indicate t he transmission of a data0 or data1 packet. the bits correspond as follows: c0 - ep0rd c1 - ep0wr c2 - ep1wr c3 - ep2wr c4 - ep3rd c5 - ep4rd r/w 0 usbd_config offset = 0x0020 bit31302928272625242322212019181716151413121110 9 8 7 6 5 4 3 2 1 0 cfgdata def.00000000000000000000000000000000 bits name description r/w default 31:8 ? reserved. should be cleared. r/w 0 7:0 cfgdata configuration data byte. use this field to write the configuration data block to the controller one byte at a time. r/w 0 bit:7654 3 210 byte 0 endpoint number 0 1 0 0 byte 1 0 0 type direction max packet size[9:7] byte 2 max packet size[6:0] 0 byte 3 0 0 0 0 0 0 0 0 byte 4 0 0 0 0 fifo number bits name description r/w default
amd alchemy? au1000? processor data book - preliminary 99 usb device controller 30360d the configuration fields are described in table 6-8. after the controller is removed from reset, the device configuration data must be written to the usbd_config register in order beginning with byte 0. bytes are written individually using unsigned 32-bit words, as shown the following example code: for (i=0; i<25; i++) *usbd_config = (unsigned int) cfg_data_bytes[i]; table 6-8. endpoint configuration field descriptions field description endpoint number although the endpoint number ranges fr om 0 to 15, only endpoints 0, 1, 2, 3, and 4 are sup- ported. it is highly recommended that the example values in table 6-9 be used for this field. type endpoint type. 00 control 01 isochronous 10 bulk 11 interrupt direction endpoint direction. (does not apply to control endpoints.) 0 out 1 in max packet size maximum packet size (in bytes). note that for control, bulk, and interrupt endpoints, the maximum packet size is limited to 64 bytes. only isoc hronous endpoints can accept packets up to 1023 bytes. 000 0000 000 = 0 bytes 000 0000 001 = 1 byte ... 111 1111 111 = 1023 bytes fifo number this field designates whic h fifo the endpoint uses. for endpoint 0 this field is ignored since end- point 0 always uses fifos 0 and 1. it is highly recommended that the example values in table 6- 9 be used for this field.
100 amd alchemy? au1000? processor data book - preliminary usb device controller 30360d an example configuration data block is shown in table 6-9. table 6-9. example endpoint configuration data block byte value description 0 0000_0100 endpoint number = 0 type = control direction = bidirectional max packet size = 64 bytes fifos 0 and 1 1 0000_0000 2 1000_0000 3 0000_0000 4 0000_0000 5 0001_0100 endpoint number = 1 type = interrupt direction = in max packet size = 64 bytes fifo 2 6 0011_1000 7 1000_0000 8 0000_0000 9 0000_0010 10 0010_0100 endpoint number = 2 ty p e = b u l k direction = in max packet size = 64 bytes fifo 3 11 0010_1000 12 1000_0000 13 0000_0000 14 0000_0011 15 0011_0100 endpoint number = 3 ty p e = b u l k direction = out max packet size = 64 bytes fifo 4 16 0010_0000 17 1000_0000 18 0000_0000 19 0000_0100 20 0100_0100 endpoint number = 4 ty p e = b u l k direction = out max packet size = 64 bytes fifo 5 21 0010_0000 22 1000_0000 23 0000_0000 24 0000_0101
amd alchemy? au1000? processor data book - preliminary 101 usb device controller 30360d 6.3.4 endpoint control registers the endpoint control registers define parameters a nd reflect operational conditions for each endpoint. usbd_ep0cs offset = 0x0024 bit31302928272625242322212019181716151413121110 9 8 7 6 5 4 3 2 1 0 su n a b sz fs def.00000000000000000000000000000000 usbd_ep1cs offset = 0x0028 usbd_ep2cs offset = 0x002c bit31302928272625242322212019181716151413121110 9 8 7 6 5 4 3 2 1 0 su n a sz fs def.00000000000000000000000000000000 usbd_ep3cs offset = 0x0030 usbd_ep4cs offset = 0x0034 bit31302928272625242322212019181716151413121110 9 8 7 6 5 4 3 2 1 0 su n a fs def.00000000000000000000000000000000 bits name description r/w default 31:15 ? reserved. should be cleared. r/w 0 14 su setup received. this bit is set when a setup packet is received from the host. it is only valid for ep 0. r0 13 n nak. this bit is set when an operation does not complete successfully or when data in a receive fifo should be ignored. for most cases this implies a returned nak in response to a data packet or an incorrect crc. r0 12 a ack. this bit is set when an operation completes successfully. most of the time this means that the host returned an ack to a data (or setup) packet or that a packet was received correctly and an ack returned to the host. isochronous data and setup packets deviate from this model. for these types of packets the a bit i ndicates successful transmission or reception but no ack is returned or expected. r0 11 b alternate ack. set when a data frame is correctly received on endpoint 0. (b is not present on other endpoints.) r0 10:1 sz size. the sz field specifies the data size of an in transfer. the sz field applies only to endpoints 0, 1, and 2. r/w 0 0 fs force stall. setting this bit places the endpoint in a stalled condition. any transaction directed to the endpoint is answered with a stall response. stall is typically used to indicate that the endpoint has halted. note that a clear feature command received via the usb does not clear a stall con- dition forced by this bit. r/w 0
102 amd alchemy? au1000? processor data book - preliminary usb device controller 30360d 6.3.5 current frame number this register provides the current frame number from the start of frame packet. 6.3.6 fifo status registers each fifo has a status regist er that indicates the current state and any e rror conditions. the usb fifos are 1-byte wide and eight bytes deep. usbd_framenum - current frame number offset = 0x0038 bit31302928272625242322212019181716151413121110 9 8 7 6 5 4 3 2 1 0 fn def.00000000000000000000000000000000 bits name description r/w default 31:11 ? reserved. should be cleared. r 0 10:0 fn frame number. this field contains the frame number from the start of frame packet. r0 usbd_ep0rdstat offset = 0x0040 usbd_ep0wrstat offset = 0x0044 usbd_ep1wrstat offset = 0x0048 usbd_ep2wrstat offset = 0x004c usbd_ep3rdstat offset = 0x0050 usbd_ep4rdstat offset = 0x0054 bit31302928272625242322212019181716151413121110 9 8 7 6 5 4 3 2 1 0 fl uf of fcnt def.00000000000000000000000000000000 bits name description r/w default 31:7 ? reserved. should be cleared. r/w 0 6 fl flush fifo. setting this bit flus hes the corresponding fifo and discards any data contained in it. w0 5 uf underflow flag. set when attempting a read from an empty fifo. clear this flag by writing a 1 to it. r/w 0 4 of overflow flag. set if a byte is written to a full fifo. clear this flag by writ- ing a 1 to it. r/w 0 3:0 fcnt fifo count. reflects the current number of bytes (0 to 8) in the corre- sponding fifo. r
amd alchemy? au1000? processor data book - preliminary 103 usb device controller 30360d 6.3.7 device controller enable register the usb device controller enable register ( usbd_enable ) controls the clocks and reset to the device controller. the pro- grammer should first enable clocks before enabling the device controller. to bring the usb device out of reset, follow these steps: 1) set the ce bit to enable clocks. 2) delay for a period greater than or equal to 1 s. 3) set the e bit to enable the peripheral. 4) delay at least 1 s before programming any registers in the peripheral. 6.3.8 programming considerations 6.3.8.1 removing the controller from reset the following sequence of operations must be applied to remove the controller from reset. 1) write a 0x0002 to the usbd_enable register to enable the clocks. 2) wait 1 s. 3) write a 0x0003 to the usbd_enable register to remove the controller from reset. 4) wait 1s. 5) write 25 bytes of configuration data to the usbd_config register. there are no special constraints on entering the reset state: one write to the usbd_enable register may be used to turn the clocks off and reset the controller. note: accessing the endpoint control registers ( usbd_ep n cs) , frame number register ( usbd_framenum ) or configuration data register ( usbd_config ) while the usb device is in su spend mode will result in a system bus deadlock. this will inhibit any further operation of the cpu, including ejtag debugger operation. 6.3.8.2 latency requirements the time from reception of a token such as in or out unti l the controller must source the corresponding data frame is very short. it is not practical to wait for a token before preparing the buffer for the response. buffers must be posted before the token is received. the token itself is not passed to the buffer?only data and setup frames are transferred. when a data or setup frame is received the difference between an out and a setup can be determined by examining the su bit in the usbd_ep0cs register. (only endpoint 0 should receive setup packets.) if an in endpoint is enabled and no data is available in the fifo the endpoint will nak. underrunning the fifo during a transfer (after the first byte has been written to the fifo) will result in a bit stuff error. usbd_enable offset = 0x0058 bit31302928272625242322212019181716151413121110 9 8 7 6 5 4 3 2 1 0 ce e def.0000000000000000000000 0000000000 bits name description r/w default 31:2 ? reserved. should be cleared. w 0 1 ce clock enable. clearing this bit disabl es all clocks to the usb device core. setting this bit allows normal operation. w0 0 e enable. when this bit is cleared the devi ce controller will be held in reset. setting this bit enables normal operation. w0
104 amd alchemy? au1000? processor data book - preliminary usb device controller 30360d 6.3.8.3 using dma dma should be used for all transfers with the exception of the fifo cleanout described below for out transactions. for in transactions the size in the usbd_ep n cs register should be set to maxpacket for all but the last buffer and to the actual remaining transfer size for the last packet. the dma size must be set to match usbd_ep n cs before the dma is enabled for proper frame transmission. if the last buffer of an in series is a full maxpacket in length it may be necessary to set the size in the usbd_ep n cs reg- ister to zero and write a byte to the fifo to enable the transmi ssion of a zero length data frame since this is often the indi- cator for end-of-transfer. in this case the fifo mu st be cleared before the next buffer is set up. for out endpoints the dma may be programmed to a larger size than a transfer will use. when the endpoint completes the fifo should be examined to see if there are any remaini ng bytes available. these bytes must be read from the fifo under program control since the dma will not receive a request when less than 4 bytes are in the fifo. for endpoint zero it is necessary to keep a dma buffer enabled at all times since setup and out transactions can come at any time. the user should implement a circular buffer and ex tract transactions from this buffer in software, rather than trying to have the dma place transactions into separate buffers. 6.3.8.4 servici ng interrupts when an interrupt is received the usbd_intstat register should be read to determine the cause of the interrupt. once the interrupt has been serviced the usbd_intstat register should be written with the same value to clear the interrupt. when an in or out transaction is completed the device controller will nak all further in/out tokens until the interrupt is cleared by writing the usbd_intstat register. this allows the interrupt service r outine time to drain the fifo and set up for the next transaction rather than concatenating data from se parate transactions. setup packets can never be delayed with nak. for bulk, isochronous, and interrupt endpoints the a and n flags are somewhat redundant. only one of them should be set for a given transaction. for the control endpoint the flags are broken out to provide separate feedback for various phases of control transactions. this is necessary since only the in and out phases can be paused with naks. setup packets must be absorbed grace- fully at all times. the a flag (ack) is set to indicate succe ssful reception of out or setup packets. the b flag (alternate ack) is set to indi- cate successful reception of out data only. (setup packets do no t affect this flag.) the n flag (nak) is set to indicate an unsuccessful attempt to send data in response to an in token. this combination of flags allows all situations to be decod ed. the most complex of these is when a setup packet immedi- ately follows an out phase used to acknowledge the previous transaction. without this separation the acknowledgement would be lost. 6.3.8.5 automatic execution of commands some standard setup commands directed at endpoint zero are automatically serviced by the usb device hardware. these commands are still passed to the memory buffer. no further action is required to service these commands although they may be used to signal state changes within the software. the following commands are automatically serviced: set address set/clear feature set/get configuration set/get interface get status 6.3.8.6 detecting usb reset the usb device controller does not provide a way to detect re set on the usb. it is recommended that if a device needs to change state on reset it should use the reception of a set address command to indicate th at a reset has occurred.
amd alchemy? au1000? processor data book - preliminary 105 usb device controller 30360d 6.3.8.7 automatic suspension if the usb device is idle for more than 5 ms, the device cont roller enters a suspend state. in this state the device controller does not consume data. a rising edge suspend interrupt is provided to inform the cpu when this occurs. the suspend interrupt may also be used to detect the exit from suspend by using the falling edge of the interrupt. note: because the usb device controller will suspend itself if left idle, the usb device confi guration routine (including pro- gramming the interrupt controller to recognize reques t and suspend interrupts from the usb device) must be fully com- pleted within 5 ms of bringing the peripheral out of its reset state. 6.3.8.8 re-establishing a connection after reset during software initialization of the usb device controller, th e usbdp and usbdm signals do not automatically enter a dis- connect-bus state in which both signals go low for more than 2. 5 s. instead, after a runtime or hardware reset of the sys- tem, the signals stay in a connect-bus state in which us bdp remains high and usbdm remains low. this prevents the usb host from recognizing the need to establish a new bus enumeration, and the logical communication flow remains dis- rupted. to re-establish logical communication afte r reset, system in itialization software can contro l a gpio signal to temporarily (more than 2.5 s) disable power to usbdp. it is recommended to use the gpio to toggle an ldo (low drop-out) voltage regulator placed between the usb power supply ( vbus) and the pull-up resistor attached to usbdp. 6.3.9 programming examples for usb device 6.3.9.1 initialization 1) configure 48 mhz usb device clock from aux pll. sys_auxpll = 16; // set the aux pll to 192 mhz (12 mhz x 16) sys_freqctrl0 |= 0x3; // enable freq0 and select aux pll as the freq0 source sys_clksrc |= 0xb; // divide freq0 by 4 to obtain 48 mhz, and select freq0 as the usb clock 2) enable usb device controller. usbd_enable = 0x02; // enable usbd clocks wait at least 1 s; usbd_enable = 0x03; // remove reset from usbd controller wait at least 1 s; 3) write 25-byte configuration data to the configuration register. for( i = 0; i < 25; ++i ) { usbd_config = (unsigned int) config_data_bytes[i]; } wait at least 1 s; 4) set up endpoint control registers (example). usbd_ep0cs = 64 << 1; // set endpoint 0 maxpacket usbd_ep1cs = 8 << 1; // set endpoint 1 maxpacket usbd_ep2cs = 8 << 1; // set endpoint 2 maxpacket usbd_ep3cs = 8 << 1; // set endpoint 3 maxpacket usbd_ep4cs = 8 << 1; // set endpoint 4 maxpacket 5) clear fifo status registers. // clear overflow flag, underflow flag, flush fifo usbd_ep0rdstat = 0x70; usbd_ep0wrstat = 0x70; usbd_ep1wrstat = 0x70; usbd_ep2wrstat = 0x70; usbd_ep3rdstat = 0x70; usbd_ep4rdstat = 0x70;
106 amd alchemy? au1000? processor data book - preliminary usb device controller 30360d 6) configure dma channels. // assign a dma channel for endpoint 0 receive and build multiple buffer descriptors // assign a dma channel for endpoint 0 transmit and build multiple buffer descriptors // assign a dma channel for endpoint 1 transmit and build multiple buffer descriptors, if necessary // assign a dma channel for endpoint 2 transmit and build multiple buffer descriptors, if necessary // assign a dma channel for endpoint 3 receive and build multiple buffer descriptors, if necessary // assign a dma channel for endpoint 4 receive and build multiple buffer descriptors, if necessary 7) configure the interrupt type for the usb device request (interrupt controller 0, number 24) as high-level. 8) configure the interrupt type for the usb device suspend (interrupt controller 0, number 25) as rising-edge. 9) start the endpoint 0 receive dma. 10) enable usb interrupts. usbd_inten = 0x0000003f; // enable transfer-complete interrupts 6.3.9.2 interrupt handler the steps to handle an interrupt are shown below. this example handler is for a general usb application and may not be sufficient for a specific application. the handle r must be installed before interrupts are enabled. 1) obtain the usbd interrupt status. status = usbd_intstat// obtain usbd_intstat 2) execute each interrupt condition. // check if endpoint transfer complete { // if ep0rd completed, execute the process for ep0rd. // if ep0wr completed, execute the process for ep0wr. // if ep1wr completed, execute the process for ep1wr. // if ep2wr completed, execute the process for ep2wr. // if ep3rd completed, execute the process for ep3rd. // if ep4rd completed, execute the process for ep4rd. } 3) clear the usbd interrupt status. usbd_intstat = status; // clear interrupts
amd alchemy? au1000? processor data book - preliminary 107 usb device controller 30360d 6.3.10 hardware considerations table 6-10 shows the signals associated with the usb device. the usb root hub port pins have usb 1.1 compliant drivers with the addition of the external circuitry noted in the signal description. the usb device implementation is full speed with the required termination noted in table 6-10. low speed is not supported. for changing pin functionality please refer to the sys_pinfunc register in section 7.3 "general purpose i/o and pin func- tionality" on page 183. table 6-10. usb device signals signal input/output description usbdp io positive signal of differential usb device driver. requires a 1.5 kohm pull-up resistor to denote a full speed device. also requires an external esd protection diode (transient voltage suppressor) to be usb 1.1 compliant. termination note: requires an external 20 ohmresistor placed in series within 0.5 inches of the part. muxed with usbh0p. usbdm io negative signal of differential usb device driver. requires an external esd pro- tection diode (transient voltage suppressor) to be usb 1.1 compliant. termination note: requires an external 20 ohm resistor placed in series within 0.5 inches of the part. muxed with usbh0m.
108 amd alchemy? au1000? processor data book - preliminary irda 30360d 6.4 irda t the irda (infrared data association) peripheral is a serial devi ce that uses an infrared serial bus. features of this periph- eral are: fir, mir, and sir modes supported integrated physical layer (phy) implementation - only an infrared transceiver is needed. integrated dma for block transfer of packet data to/from memory support for both big endian and little endian memory addressing 16-bit or 32-bit hardware crc generation and detection interrupt support on send and receive of buffer the operating modes and standards supported are listed in table 6-11. 6.4.1 irda registers the irda peripheral is programmed via a block of registers with a base address as shown in table 6-12. the register set index is described in table 6-13. table 6-11. irda modes supported mode speed compliance sir 2.4 to 115.2 kbps irda 1.0 mir 1.152 mbps irda 1. 1 with error detection fir 4.0 mbps irda 1.1 with error detection table 6-12. irda base address name physical base address kseg1 base address irda_base 0x0_1030_0000 0x_b030_0000 table 6-13. irda registers offset register name description 0x0000 ir_rngptrstat infrared ring pointer status 0x0004 ir_rngbsadrh infrared ring base address high register 0x0008 ir_rngbsadrl infrared ring base address low register 0x000c ir_ringsize infrared ring size register 0x0010 ir_rngprompt infrared ring prompt register 0x0014 ir_rngadrcmp infrared ring address compare register 0x0018 ir_intclear irda interrupt clear register 0x0020 ir_config1 infrared configuration 1 register 0x0024 ir_sirflags infrared sir flags register 0x0028 ir_statusen infrared status/enable register 0x002c ir_rdphycfg infrared read phy configuration register 0x0030 ir_wrphycfg infrared write phy configuration register 0x0034 ir_maxpktlen infrared maximum packet length register 0x0038 ir_rxbytecnt infrared received byte count register 0x003c ir_config2 infrared configuration register 2 0x0040 ir_enable infrared interface configuration register
amd alchemy? au1000? processor data book - preliminary 109 irda 30360d 6.4.1.1 infrared ring pointer status register this read-only register gives the current indices for both the tr ansmit and receive ring buffer pointers. the ring buffers form one contiguous memory block with the receive ring buffer beginning at the ring base address and the transmit ring buffer following afterward. 6.4.1.2 infrared ring base address high register this register defines the base address of the transmit and rece ive ring buffers. the receive ring buffer begins at the speci- fied base address; the transmit ring buffer begins at base address + 512 bytes. 6.4.1.3 infrared ring base address low register this register defines the base address of the transmit and rece ive ring buffers. the receive ring buffer begins at the speci- fied base address; the transmit ring buffer begins at base address + 512 bytes. ir_rngptrstat - infrared ring pointer status offset = 0x0000 bit31302928272625242322212019181716151413121110 9 8 7 6 5 4 3 2 1 0 trpi rrpi def.00000000000000000100000000000000 bits name description r/w default 31:15 ? reserved. read as 0. r 0 14 ? reserved. read as 1. r 1 13:8 trpi transmit ring pointer index. gives the current pointer location in the transmit ring buffer. r0 7:6 ? reserved. always read as 0. r 0 5:0 rrpi receive ring pointer index. gives the current pointer location in the receive ring buffer. r0 ir_rngbsadrh - infrared ring base address high register offset = 0x0004 bit31302928272625242322212019181716151413121110 9 8 7 6 5 4 3 2 1 0 rbah def.00000000000000000000000000000000 bits name description r/w default 31:6 ? reserved. read/written as 0. r/w 0 5:0 rbah ring buffer base address bits [31:26]. r/w 0 ir_rngbsadrl - infrared ring base address low register offset = 0x0008 bit31302928272625242322212019181716151413121110 9 8 7 6 5 4 3 2 1 0 rbal def.00000000000000000000000000000000 bits name description r/w default 31:16 ? reserved. read/written as 0. r/w 0 15:0 rbal ring buffer base address bits [25:10]. r/w 0
110 amd alchemy? au1000? processor data book - preliminary irda 30360d 6.4.1.4 infrared ring size register this register defines the size for both the transmit and receive ring buffers. 6.4.1.5 infrared ring prompt register writing this register forces the infrared controller to read t he ownership bits of the transmit and receive ring buffers. read- ing this register returns a value of 0x_0000_ffff. 6.4.1.6 infrared ring address compare register setting the address field in this register will define which irda packets to accept. note: this feature must be enabled by setting en = 1. ir_ringsize - infrared ring size register offset = 0x000c bit31302928272625242322212019181716151413121110 9 8 7 6 5 4 3 2 1 0 trbs rrbs def.00000000000000000000000000000000 bits name description r/w default 31:16 ? reserved. read/written as 0. r/w 0 15:12 trbs transmit ring buffer size and receive ring buffer size. each ring buffer size is programmed as follows: 00004 entries (default) 00018 entries 001116 entries 011132 entries 111164 entries all other values are not valid. r/w 0 11:8 rrbs r/w 0 7:0 ? reserved. read/written as 0. r/w 0 ir_rngprompt - infrared ring prompt register offset = 0x0010 bit31302928272625242322212019181716151413121110 9 8 7 6 5 4 3 2 1 0 d/c def.xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx bits name description r/w default 31:16 ? reserved. should be written as 0. w unpred 15:0 d/c don?t care. w unpred ir_rngadrcmp - infrared ring address compare register offset = 0x0014 bit31302928272625242322212019181716151413121110 9 8 7 6 5 4 3 2 1 0 en addr def.00000000000000000000000000000000 bits name description r/w default 31:16 ? reserved. read/written as 0. r 0 15 en address comparison enable. 0 comparison disabled. 1 comparison enabled. r/w 0 14:8 ? reserved. read/written as 0. r/w 0 7:0 addr irda packet address to compare. r/w 0
amd alchemy? au1000? processor data book - preliminary 111 irda 30360d 6.4.1.7 irda interrupt clear writing to this register will clear all pending irda interrupts. 6.4.1.8 infrared configuration register 1 this register defines general setup parameters for the irda controller. ir_intclear - irda interrupt clear offset = 0x0018 bit31302928272625242322212019181716151413121110 9 8 7 6 5 4 3 2 1 0 ic def.xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx bits name description r/w default 31:0 ic interrupt clear. any write to th is register will cl ear all pending irda interrupts. w unpred ir_config1 - infrared configuration register 1 offset = 0x0020 bit31302928272625242322212019181716151413121110 9 8 7 6 5 4 3 2 1 0 el il te re me ra td cm fi mi si sf st ti ri def.00000000000000000000000000000000 bits name description r/w default 31:16 ? reserved. read/written as 0. r/w 0 15 el enable external transmit while in loopback. r/w 0 14 il enable internal loopback (fir only). r/w 0 13 ? reserved. read/written as 0. r/w 0 12 te transmit enable. unless in loopbac k mode, only one transfer direction (transmit or receive) can be enabled at one time. r/w 0 11 re receive enable. unless in loopback mode, only one transfer direction (transmit or receive) can be enabled at one time. r/w 0 10 me dma enable. when set me allows dma access to system memory by the irda controller. the irda has its own dma controller. this bit should always be set for normal operation. r/w 0 9 ra receive all small/runt packets of size less than 4 bytes (sir mode only). r/w 0 8 td transparency destuffing disable for sir receive filter. 0 destuffing enabled. 1 destuffing disabled. r/w 0 7 cm cyclical redundancy check (crc) mode. 0 32-bit crc 1 16-bit crc r/w 0 6 fi fast infrared mode enable (fir). when this bit is set the irfirsel output will be a 1 r/w 0 5 mi medium infrared mode enable (mir). when this bit is set the irfirsel output will be a 1 r/w 0 4 si slow infrared mode enable (sir). when this bit is set the irfirsel output will be a 0 r/w 0 3 sf enable sir byte filter on the receiver (sir mode only). r/w 0 2 st enable sir filter when not in sir mode (test). r/w 0 1 ti invert transmit led signal. r/w 0 0 ri invert receive led signal. r/w 0
112 amd alchemy? au1000? processor data book - preliminary irda 30360d 6.4.1.9 infrared sir flags register this register returns bit sequences for start- of-frame and end-of-frame of an irda packet. 6.4.1.10 infrared st atus/enable register this register defines enabling/disabling of the physical (phy) layer and gives programming status for the irda controller as defined by infrared configuration register 1 ( ir_config1 ). ir_sirflags - infrared sir flags register offset = 0x0024 bit31302928272625242322212019181716151413121110 9 8 7 6 5 4 3 2 1 0 fs hs def.00000000000000001100000111000000 bits name description r/w default 31:16 ? reserved. read as 0. r 0 15:8 fs footer bit sequence for end-of-frame. r 0xc1 7:0 hs header bit sequence for start-of-frame. r 0xc0 ir_statusen - infrared status/enable register offset = 0x0028 bit31302928272625242322212019181716151413121110 9 8 7 6 5 4 3 2 1 0 e ce fv mv sv ts rs cs def.00000000000000000000000011111111 bits name description r/w default 31:16 ? reserved. read/written as 0. r/w 0 15 e enable phy layer. r/w 0 14 ce configuration error . this bit is set when more than one operating mode (sir, mir, or fir) is enabled simultaneously. r0 13 fv valid fir mode configuration. r 0 12 mv valid mir mode configuration. r 0 11 sv valid sir mode configuration. r 0 10 ts status of transmit enable (te) bit. r 0 9 rs status of receive enable . r 0 8 cs status of cyclical redundancy check mode (cm) bit. r 0 7:0 ? reserved. read as 1. r 0xff
amd alchemy? au1000? processor data book - preliminary 113 irda 30360d 6.4.1.11 infrared read ph y configuration register this register returns the setti ngs of the the last value in ir_wrphycfg when bit 15 (enable) of the ir_statusen register is 0. when enable is set, a write to ir_wrphycfg will not update into ir_rdphycfg until enable is 0 again. 6.4.1.12 infrared write ph y configuration register this register defines the settin gs of the physical layer (phy) interface. when read this register returns the last value writte n to it. the status of these values ma y be read by the infrared read phy configuration register, ir_rdphycfg when bit 15 (enable) of the ir_statusen register is 0. ir_rdphycfg - infrared read phy configuration register offset = 0x002c bit31302928272625242322212019181716151413121110 9 8 7 6 5 4 3 2 1 0 br pw p def.00000000000000000100000000000000 bits name description r/w default 31:16 ? reserved. read as 0. r 0 15:10 br baud rate (see ?programming considerations? on page 116). r 0 9:5 pw pulse width (see ?programming considerations? on page 116). r 0 4:0 p this register will determine the num ber of preamble bytes to send for fir, or start flags for mir. it should be interpreted as 1 less than the actual number of preamble bytes/start flags required (i.e. setting this field to 1 will cause 2 start flags to be sent in mir mode). this field does not apply to sir. r0 ir_wrphycfg - infrared write phy configuration register offset = 0x0030 bit31302928272625242322212019181716151413121110 9 8 7 6 5 4 3 2 1 0 br pw p def.00000000000000000100000000000000 bits name description r/w default 31:16 ? reserved. read/written as 0. r/w 0 15:10 br baud rate (see ?programming considerations? on page 116). r/w 0 9:5 pw pulse width (see ?programming considerations? on page 116). r/w 0 4:0 p this register will determine the num ber of preamble bytes to send for fir, or start flags for mir. it should be interpreted as 1 less than the actual number of preamble bytes/start flags required (i.e. setting this field to 1 will cause 2 start flags to be sent in mir mode). this field does not apply to sir. r/w 0
114 amd alchemy? au1000? processor data book - preliminary irda 30360d 6.4.1.13 infrared maximum packet length register this register defines the maximum length of a received irda packet. 6.4.1.14 infrared recei ve byte count register this register returns the current number of received bytes. 6.4.1.15 infrared configuration register 2 this register defines general setup parameters for the irda controller. ir_maxpktlen - infrared maximum pa cket length register offset = 0x0034 bit31302928272625242322212019181716151413121110 9 8 7 6 5 4 3 2 1 0 ml def.00000000000000000000000000000000 bits name description r/w default 31:13 ? reserved. read/written as 0. r/w 0 12:0 ml maximum received packet length. r/w 0 ir_rxbytecnt - infrared receive byte count register offset = 0x0038 bit31302928272625242322212019181716151413121110 9 8 7 6 5 4 3 2 1 0 rbcr def.00000000000000000000000000000000 bits name description r/w default 31:13 ? reserved. read as 0. r 0 12:0 rbcr received byte count. r 0 ir_config2 - infrared configuration register 2 offset = 0x003c bit31302928272625242322212019181716151413121110 9 8 7 6 5 4 3 2 1 0 ie fs da dp cs p mi def.00000000000000001111111000000011 bits name description r/w default 31:16 ? reserved. read/written as 0. r/w 0 15:9 ? reserved. read as 1. r 0x7f 8 ie interrupt enable. setting this bit will allow interrupts to be generated when a ring buffer has been transmitted or re ceived. writing to the ir_intclear register will clear all pending interrupts. r/w 0 7:6 fs filter selection for finite impulse response dpll. 00 highest filter 01 medium high filter 10 medium low filter 11 lowest filter r/w 0x0 5 da disable adjacent pulse width packet circuit in the fir dpll. 0 circuit enabled 1 circuit disabled r/w 0 4 dp disable pulse width adjustmen t circuit in the fir dpll. r/w 0
amd alchemy? au1000? processor data book - preliminary 115 irda 30360d 6.4.1.16 infrared enable register this register defines the irda peripheral interface se tup and has a bit to enable clocks to the irda module. the correct routine for bringing the irda out of reset is as follows: 1) set the ce bit to enable clocks with the hc, c, and e bit set appropriately. 3:2 cs phy layer clock speed. 00 40 mhz 01 48 mhz 10 56 mhz 11 64 mhz note that the irda clock must be conf igured to match value set in cs. the irda clock is programmed from the clock generator; see section 7.1 "clocks" on page 168. r/w 0x0 1 p one receive pin mode. 0 two pins for receive 1 one pin each for receive and speed select (slow or fast) r/w 0 0 mi mode inversion (when p=1). 0 fast speed is chosen by asserting speed select low. 1 fast speed is chosen by asserting speed select high. r/w 0 ir_enable - infrared enable register offset = 0x0040 bit31302928272625242322212019181716151413121110 9 8 7 6 5 4 3 2 1 0 hc ce c e def.00000000000000000000000000000000 bits name description r/w default 31:4 ? reserved. read/written as 0. r/w 0 3 hc half clock speed for irda clock. 0 clock runs at full system bus frequency. 1 clock runs at one-half system bus frequency. note that hc is not just for power savings. hc must be set when the sys- tem bus is greater than 100 mhz. r/w 0 2 ce clock enable for the irda module. 0 disable clocks. 1 enable clocks. r/w 0 1 c coherent. 0 memory accesses are marked non coherent 1 memory accesses are marked coherent for more information on coherency see section 2.8.2 "sbus coherency model" on page 41 for more information on coherency. r/w 1 0 e endian mode. 0 little endian 1 big endian r/w 1 bits name description r/w default
116 amd alchemy? au1000? processor data book - preliminary irda 30360d 6.4.2 hardware considerations table 6-14 describes the connection between the irda peripheral and the external transceiver. for changing pin functionality refer to the sys_pinfunc register in section 7.3 "general purpose i/o and pin functionality" on page 183. 6.4.3 programming considerations 6.4.3.1 initialization first the irda clock must be set to match the cs setting in the ir_config2 register. please see section 7.1 "clocks" on page 168 for more information. second, enable peripheral logic by programming the ir_enable register: hc should be set to 1 for low power or if the sys- tem bus is greater than 100 mhz, ce must be set to 1 to e nable the peripheral logic, c should be set to 1 for dcache to respond to irda accesses on the system bus if it has t he data, and e should be set for the appropriate endianess. next, the sys_pinfunc register bits must be set to the alternate (irda) function: irf can optionally be set to 1 to enable irda to drive the firsel pin (this pin is not required if extern al logic takes care of setting the transceiver speed). ird must be set to 0 to enable data transmission through the irtxd pin. 6.4.3.2 power management the hc bit in the ir_enable register can be used to run the irda at half the system bus. the ce s hould be disabled when not using the irda to gate clocks from this peripheral. table 6-14. irda hardware connections signal input/output description irdatx o serial irda output. muxed with gpio[19]. irdarx i serial irda input. irfirsel o output which will signal at which speed t he irda is currently set. this signal is not necessary for irda operation. this pin will be driven high when irda is configured for fir or mir. this pin will be driven low for sir mode. muxed with gpio[15] which controls the pi n out of hardware reset, runtime reset and sleep.
amd alchemy? au1000? processor data book - preliminary 117 irda 30360d 6.4.3.3 programming notes irda can be operated at speeds ranging from 2400 bps to 4 mb ps. table 6-15 shows the proper parameters to configure communications speed and irda mode. table 6-16, table 6-17 and table 6-18 show the ordered steps for programming the irda peripheral for each mode. table 6-15. irda phy configuration table mode speed (bps) baud rate pulse width preamble/start flags min nom max sir 2400 47 0 12 12 n/a sir 9600 11 0 12 12 n/a sir 19200 5 1 12 12 n/a sir 38400 2 3 12 14 n/a sir 57600 1 5 12 16 n/a sir 115200 0 11 12 20 n/a mir 1150000 0 n/a 8 n/a 2 (p field = 1) fir 4000000 0 n/a n/a n/a 16 (p field = 15) table 6-16. fast infrared mode (fir) step register value notes 1 ir_enable 0x000e enable half clock speed (hc), clocks (ce), coherency (c), and little endian (e). 2 ir_statusen 0x0000 clear bit e to allow peripheral programming (disable irda). 3 ir_maxpktlen 0x0020 32 bytes maximum per packet 4 ir_wrphycfg 0x000f 16 preamble bytes (p field requires 1 less than number needed) 5 ir_config1 0x1c40 enable transmitter (te), receiver (re), memory scheduler (me), and fast infrared mode (fi). note: set pin inversion bits (ti and/or ri) accordingly for proper transceiver operation. 6 ir_rngbsadrl user defined write the physical address of ring buffer memory. note: the final address must have zeros for address bits 9:0 (i.e. the address must reside on a 1 kbyte boundary). 7 ir_rngbsadrh user defined write the physical address of ring buffer memory. note: the final address must have zeros for address bits 9:0 (i.e. the address must reside on a 1 kbyte boundary). 8 ir_ringsize user defined write the desired ring size. 9 ir_config2 0x0004 set the phy clock speed to 48 mhz. 10 ir_statusen 0x8000 set bit e to enable the peripheral, then read register again for cor- rect status (should equal 0xa6ff). 11 ir_rngprompt 0x0000 write a zero to this register to start the irda transfers.
118 amd alchemy? au1000? processor data book - preliminary irda 30360d table 6-17. medium infrared mode (mir) step register value notes 1 ir_enable 0x000e enable half clock speed (h c), clocks (ce), coherency (c), and little endian (e). 2 ir_statusen 0x0000 clear bit e to allow peripheral programming (disable irda). 3 ir_maxpktlen 0x0020 32 bytes maximum per packet 4 ir_wrphycfg 0x0101 1 preamble byte (p field requires one less than number needed), pulse width = 8 5 ir_config1 0x1c20 enable transmitter (te) , receiver (re), memory scheduler (me), and medium infrared mode (mi). note: set pin inversion bits (ti and/or ri) accordingly for proper transceiver operation. 6 ir_rngbsadrl user defined write the physical address of ring buffer memory. note: the final address must have zeros for address bits 9:0 (i.e. the address must reside on a 1 kbyte boundary). 7 ir_rngbsadrh user defined write the physical address of ring buffer memory. note: the final address must have zeros for address bits 9:0 (i.e. the address must reside on a 1 kbyte boundary). 8 ir_ringsize user defined write the desired ring size. 9 ir_config2 0x0004 set the phy clock speed to 48 mhz. 10 ir_statusen 0x8000 set bit e to enable the peripheral, then read register again for cor- rect status (should equal 0x96ff). 11 ir_rngprompt 0x0000 write a zero to this register to start the irda transfers.
amd alchemy? au1000? processor data book - preliminary 119 irda 30360d ring buffers the irda controller is designed to allow the cpu to access th e ir media through a system of ?rings? set up in memory. each ring entry corresponds to a lan packet and stores inform ation and status about that packet as well as the physical address of where the data for that packet is stored. the ring area is split into two areas: transmit and receive. the receive ring starts at the base address location (specified by the cont ents of the ring base address registers) and the transmit ring starts at the base address + 512 bytes (decimal). each ring entry contains 8 bytes with a maximum of 64 ring entries in each of the transmit and/or receive ring areas. the ac tual number of entries used is programmed via the ir_ringsize regis- ter. the format for each transmit ring entry is shows in figure 6-2. figure 6-2. transmit ring buffer entry format table 6-18. slow infrared mode (sir) step register value notes 1 ir_enable 0x000e enable half clock speed (h c), clocks (ce), coherency (c), and little endian (e). 2 ir_statusen 0x0000 clear bit e to allow peripheral programming (disable irda). 3 ir_maxpktlen 0x0020 32 bytes maximum per packet. 4 ir_wrphycfg 0x0180 baudrate = 0 (115200), pulse width = 12. 5 ir_config1 0x1e10 enable transmitter (te) , receiver (re), memory scheduler (me), receive all runt packets (ra), and slow infrared mode (si). note: set pin inversion bits (ti and/or ri) accordingly for proper transceiver operation. 6 ir_rngbsadrl user defined write the physical address of ring buffer memory. note: the final address must have zeros for address bits 9:0 (i.e. the address must reside on a 1 kbyte boundary). 7 ir_rngbsadrh user defined write the physical address of ring buffer memory. note: the final address must have zeros for address bits 9:0 (i.e. the address must reside on a 1 kbyte boundary). 8 ir_ringsize user defined write the desired ring size. 9 ir_config2 0x0004 set the phy clock speed to 48 mhz. 10 ir_statusen 0x8000 set bit e to enable the peripheral, then read register again for cor- rect status (should equal 0x8eff). 11 ir_rngprompt 0x0000 write a zero to this register to start the irda transfers. 76543210 bit: ur fu np bc r dc o count[7:0] count[11:8] addr[7:0] addr[15:8] addr[23:16] addr[31:24] byte 0 byte 1 byte 2 byte 3 byte 4 byte 5 byte 6 byte 7
120 amd alchemy? au1000? processor data book - preliminary irda 30360d table 6-19. transmit ring buffer entry format description bits name description r/w default byte 0 bits 7:0 count[7:0] number of bytes to transmit (lowest 8 bits) r/w user assigned byte 1: bits 7:4 ? reserved. read/written as 0. r/w 0 byte 1: bits 3:0 count[11:8] number of bytes to transmit (upper 4 bits) r/w user assigned byte 2: bits 7:0 ? reserved. read/written as 0. r/w 0 byte 3: bit 7 o ownership flag. 0 user has ownership of the packet. 1 hardware has ownership of the packet and is sending the packet data to the transmitter. hardware clears this bit when the packet has been sent. r/w user assigned byte 3: bit 6 dc disable the transmit crc. 0 used for synchronous packet operation. 1 used by irda sir mode. hardware clears this bit when the packet has been sent. r/w user assigned byte 3: bit 5 bc force a bad crc. 0 normal crc operation. 1 send an ?invalid? crc flag in the packet. used to test receiver crc checking. hardware clears this bit when the packet has been sent. r/w user assigned byte 3: bit 4 np need an indication pulse. 0 normal operation. 1 transmit an indication pulse after the packet has been transmit- ted. hardware clears this bit when the packet has been sent. r/w user assigned byte 3: bit 3 fu force an underrun condition. 0 normal operation. 1 force an underrun on this packet. packet size must be greater than 18 bytes. used for testing only. r/w user assigned byte 3: bit 2 r request to disable transmitter. 0 normal operation. 1 hardware will clear ir_config1 transmit enable (te) bit after this packet has been transmitted. used to shut down the transmitter immediately after the last packet. r/w user assigned byte 3: bit 1 ? reserved. read/written as 0. r/w 0 byte 3: bit 0 ur hardware underrun error. this bit is set if a hardware underrun occurs during transmission of a packet. used only to find hardware errors. r0 byte 4: bits 7:0 addr[7:0] address of data to transmit (bits 7:0). r/w user assigned byte 5: bits 7:0 addr[15:8] address of data to transmit (bits 15:8). r/w user assigned byte 6: bits 7:0 addr[23:16] address of data to transmit (bits 23:16). r/w user assigned byte 7: bits 7:0 addr[31:24] address of data to transmit (bits 31:24). r/w user assigned
amd alchemy? au1000? processor data book - preliminary 121 irda 30360d the format for each receive ring entry is described in figure 6-3. figure 6-3. receive ring buffer entry format table 6-20. receive ring buffer entry format description bits name description r/w default byte 0 bits 7:0 count[7:0] number of bytes received (lowest 8 bits) r/w user assigned byte 1: bits 7:5 ? reserved. read/written as 0. r/w 0 byte 1: bits 4:0 count[12:8] number of bytes received (upper 5 bits) r/w user assigned byte 2: bits 7:0 ? reserved. read/written as 0. r/w 0 byte 3: bit 7 o ownership flag. 0 user has ownership of the packet. 1 hardware has ownership of the packet and is writing packet data from the receiver to memory. hardware clears this bit when the packet has been received. r/w user assigned byte 3: bit 6 pe phy layer error detected. r/w user assigned byte 3: bit 5 ce crc error detected. valid for fir and mir modes only. r/w user assigned byte 3: bit 4 ml maximum packet length reached. for sir mode, data will continue to be received in adjacent packets. however, for fir and mir modes, subsequent data will be dropped. r/w user assigned byte 3: bit 3 fo internal hardware fifo overflow. this should not occur under normal operation. r/w user assigned byte 3: bit 2 se sir error detected. if the sir filter is enabled, this flag will be set if an end flag is not received. r/w user assigned byte 3: bits 1:0 ? reserved. read/written as 0. r/w 0 byte 4: bits 7:0 addr[7:0] address of data to receive (bits 7:0). r/w user assigned byte 5: bits 7:0 addr[15:8] address of data to receive (bits 15:8). r/w user assigned byte 6: bits 7:0 addr[23:16] address of data to receive (bits 23:16). r/w user assigned byte 7: bits 7:0 addr[31:24] address of data to receive (bits 31:24). r/w user assigned 76543210 bit: fo ml ce se pe o count[7:0] count[12:8] addr[7:0] addr[15:8] addr[23:16] addr[31:24] byte 0 byte 1 byte 2 byte 3 byte 4 byte 5 byte 6 byte 7
122 amd alchemy? au1000? processor data book - preliminary irda 30360d on the transmit side the descriptors are set up and point to the data associated with them. each buffer has an ownership bit that tells the hardware it has been given control of that buffer. when the hardware has finished with a buffer it will clear th e ?o? bit. if polling this is how software can tell whether a rece ive or transit is done. when using interrupts, when the hardwar e is finished either transmitting or receiving an interrupt will be generated if they are enabled in the ir_config2 register. see section 5.0 "interrupt controller" on page 81. buffers are in a ring structure and are always accessed in sequ ence. once the controller reaches a buffer in which the own- ership bit is not set, it will stop the chaining at that point and will require the processor to "prompt" it to look at the buf fer again and restart the chaining.
amd alchemy? au1000? processor data book - preliminary 123 ethernet mac controller 30360d 6.5 ethernet mac controller the au1000 processor contains two ethernet mac devices. th e mac provides the interface between the host application and the phy layer through the media independent interface (mii). the phy layer device is external to the processor. the mac supports the protocol re quirements to meet the ethernet/ieee 802.3 s pecification. the mac operates in both half and full duplex modes. in ha lf duplex mode the mac is comp liant with section 4 of iso/ iec 8802-3 (ansi/ieee standard) and ansi/ieee 802.3. the mac provides programmable enhanced features designed to minimize host supervisio n, bus utilization and pre/post message processing. these features include ability to disable retries after a collision, dynamic fcs generation on a frame by frame basis, automatic pad field insertion and deletion to enforce minimum frame size attributes, automatic retransmis- sion and detection of collision frames. the mac can sustain tr ansmission or reception of minimal size back to back packets at full line speed with an inter-packet gap of 9.6 s for 10 mbps and 0.96 s for 100 mbps. a dedicated dma engine is implemented to support the mac so that the general purpose dma is not required. the primary attributes of the mac are: transmit and receive message data encapsulation with framing and error detection. frame boundaries are delimited and frames are synchronized. error detection is done at the physical medium transmis- sion level. media access management is supported through medium allo cation and contention resolution. this is accomplished through collision avoidance and handling. the mac handles collision per the iso 8802.3 specification. support for flow control during full duplex mode is accomplished by decoding of control frames and disabling the trans- mitter in conjunction with generation of control frames. the serial control interface supports the mii protocol to interface to an mii based phy. the mac features are: ieee 802.3, 802.3 u, 803.3x specification compliance 10/100 mbps data transfer rates ieee 802.3 compliant mi i interface to talk to an external phy full and half duplex csma/cd in half duplex flow control support for full duplex collision detection and auto retransmit on collisions in half duplex preamble generation and removal automatic 32 bit crc generation and checking optional automatic pad stripping on the receive packets. loopback support on the mii filtering modes supported on the ethernet side: ? one 48 bit perfect address ? 64 hash-filtered multicast addresses ? pass all multicast addresses ? promiscuous mode ? pass all incoming packets with a status report ? toss bad packets separate 32 bit status returned for transmit and receive packets ? jumbo packet (0x2800 bytes) ? big/little endian data format support
124 amd alchemy? au1000? processor data book - preliminary ethernet mac controller 30360d the following phy interfaces are supported: mii - ethernet 4bit parallel phy per ieee 802.3u spec mii management - 2 wire bus to cont rol and receive status from phy hpna 1.0 support across mii the control registers for the mac are used for address filterin g, packet filter for good and bad frames, 48-bit mac address with a local station address, a multicast table for filtering multicast frames and more. each register is 32 bits wide. 6.5.1 ethernet base address registers the two ethernet macs contained in t he au1000 processor are located at the base addresses shown in table 6-21. in addition, the base addresses for the enable r egisters and the mac dma registers are shown. 6.5.2 mac configuration registers the ethernet mac registers are lis ted in table 6-22. each ethernet mac has an identical register set with identical offsets from mac0_base and mac1_base . table 6-21. ethernet base addresses name physical base address kseg1 base address mac0_base 0x0_1050_0000 0x_b050_0000 mac1_base 0x0_1051_0000 0x_b051_0000 macen_base 0x0_1052_0000 0x_b052_0000 macdma0_base 0x0_1400_4000 0x_b400_4000 macdma1_base 0x0_1400_4200 0x_b400_4200 table 6-22. mac configuration register descriptions offset register name description 0x0000 mac_control operation mode and address filter 0x0004 mac_addrhigh high 16 bits of the mac physical address 0x0008 mac_addrlow lower 32 bits of the mac physical address 0x000c mac_hashhigh high 32 bits of the multicast hash address 0x0010 mac_hashlow low 32 bits of the multicast hash address 0x0014 mac_miictrl control of phy management interface 0x0018 mac_miidata data to be written or read from phy over control interface 0x001c mac_flowctrl control frame generation control 0x0020 mac_vlan1 vlan1 tag 0x0024 mac_vlan2 vlan2 tag
amd alchemy? au1000? processor data book - preliminary 125 ethernet mac controller 30360d 6.5.2.1 mac control register the mac control register establishes the receive and transmit operating modes and controls for address filtering and packet filtering. note that the pm, pr, if, hp and ho bits in the mac cont rol register will determine the address filtering mode. the ra, db, pc and pb bits will determine the packet filter mode. t he first bit of the destination address will determine if the address is a physical address (first bit = 0) or a multicast addre ss (first bit = 1). if all bits in the destination address ar e set to 1 then the address is a broadcast address. mac_control offset = 0x0000 bit31302928272625242322212019181716151413121110 9 8 7 6 5 4 3 2 1 0 ra em do lm f pm pr if pb ho hp lc db dr ap bl dc te re def.00000000000000000000000000000000 bits name description r/w default 31 ra receive all. 0 normal operation 1 all incoming packets will be received regardless of the destination address. the address filter status is reported in receive status bit filtering fail. the packet filter bit in the receive st atus is set for all error-free frames regardless of the dest ination address field. r/w 0 30 em endian mode for data buffers. 0 little endian 1 big endian r/w 0 29:24 ? reserved. should be cleared. r 0 23 do disable receive own. 0 the mac receives all packets that are given by the phy. 1 the mac disables reception of frames when the txen is asserted. the mac ignores any loop backed receive packets. this bit should be cleared when the full duplex mode bit is set or the oper- ating mode is set to other than normal mode. r/w 0 22:21 lm loopback operating mode. 00 normal mode 01 internal loopback 10 external loopback 11 reserved r/w 00 20 f full duplex mode. 0 half duplex mode 1 full duplex mode note: be sure to disable both the transmitter and receiver before changing duplex modes. r/w 0 19 pm pass all multicast. 0normal 1 all incoming frames with a multicas t destination address (first bit in the destination address field is ?1?) are received and the filter fail bit reset. incoming frames with physical address destinations are filtered according to hp (bit 13) and ho (bit 15). r/w 0 18 pr promiscuous mode. 0normal 1 any incoming valid frame is received regardless of its destination address. the filter fail bit is alwa ys cleared in promiscuous mode. r/w 1
126 amd alchemy? au1000? processor data book - preliminary ethernet mac controller 30360d 17 if inverse filtering. 0normal. 1 physical addresses are checked with inverse filtering. in other words if the address passes a perfect addres s filter, the frame is not passed; if the address fails a perfect filter, the frame is passed. this is valid only during perfect filtering mode. r/w 0 16 pb pass bad frames. 0normal. 1 all incoming frames that passed the address filtering are received including runt frames, collided fr ames, or truncated frames caused by buffer overflow. the packet filter bit is set for error fr ames that pass the address filtering. if all received bad frames are required, promiscuous mode (bit 18) should be set. r/w 0 15 ho hash only filtering mode. 0 perfect address filtering mode for physical addresses. 1 imperfect address filtering mode both for physical and multicast addresses. setting this bit is valid only if hp=1. r/w 0 14 ? reserved. should be cleared. r 0 13 hp hash/perfect filtering mode. 0 address check block does a perfect address filter of incoming frames according the address specified in the mac address register. 1 address check block does imperfect address filtering of multicast incoming frames according to the has h table specified in the multicast hash table register. if the hash on ly (ho) bit is set, then physical addresses are imperfectly filtered too. if the hash only bit (ho) is reset, then physical addresses are per fect address filtered according to the mac address register. r/w 0 12 lc late collision control. 0 abort frame transmission on a late collision. 1 enable the retransmission of the collided frame even after the colli- sion period (late collision). in either case the late collision st atus is appropriately updated in the transmit packet status. this bit is valid only when operating in half duplex mode. r/w 0 11 db disable broadcast frames. 0 forward all the broadcast frames to the application. (packet filter bit is set.) 1 disable the reception of broadcast frames. (packet filter bit is cleared.) r/w 0 10 dr disable retry. 0 the mac will attempt 16 transmissions before signaling a retry error. 1 the mac will attempt transmission of a frame only once. when a col- lision is seen on the bus, the mac will ignore the current frame and go to the next frame and a retry error will be reported in the transmit status. this bit is valid only when operating in half duplex mode. r/w 0 9 ? reserved. should be cleared. r 0 bits name description r/w default
amd alchemy? au1000? processor data book - preliminary 127 ethernet mac controller 30360d 8 ap automatic pad stripping. 0 pass all the incoming frames to the host unmodified. 1 strip the pad field on all the incoming frames if the length field is less than 46 bytes. the fcs field is also stripped, because it is computed at the transmitting station based on the data and pad field characters and will therefore be invalid for a receive frame that has had the pad characters stripped. receive frames which have a length field of 46 bytes or greater will be passed to the host unmodified (fcs is not stripped). pad stripping is done only on the ieee 802.3 formatted frames (frames with length field). r/w 0 7:6 bl backoff limit. the backoff limit determines the integer number of slot times the mac waits before rescheduli ng a transmission attempt (during retries after a collision). r/w 00 5 dc deferral check. 0 the deferral check is disabled in the mac and the mac defers indef- initely. 1 the deferral check is enabled in the mac. the mac will abort the transmission attempt if it has deferred for more than 24,288 bit times. deferring starts when the transmitter is ready to transmit, but is pre- vented from doing so because crs is active. defer time is not cumu- lative. in other words, if the transmitter defers, then transmits, collides, backs off, and then has to defer again after completion of backoff, the deferral timer resets to 0 and restarts. this bit is valid only when operating in half duplex mode. r/w 0 4 ? reserved. should be cleared. r 0 3 te transmitter enable. 0 the mac transmitter is disabled a nd will not transmit any frames on the mii interface. 1 the mac transmitter is enabled and it will transmit frames from the buffer on to the mii interface. r/w 0 2 re receiver enable. 0 the mac receiver is disabled and will not receive any frames from the mii interface. 1 the mac receiver is enabled and will receive frames from the mii interface. r/w 0 1:0 ? reserved. should be cleared. r 0 bits name description r/w default
128 amd alchemy? au1000? processor data book - preliminary ethernet mac controller 30360d 6.5.2.2 mac address high and low registers the mac address high register contains the upper 16 bits of the physical address of the mac. the mac address low register contains the lower 32 bits of the physical address of the mac. it is the responsibility of t he system designer to provide th e mac address for the system. the mac address will be compared with the destination address from the incoming frame with padr[0] (bit 0 of the mac address low register) being compared with the first bit of the destination address and pa dr[47] (bit 15 of the mac address high register) compared with the 48th bit of the destination address. example: to program the mac address 00.50.c2.0c.20.10 th e mac address registers should be programmed as follows: mac_addrhigh = 0x00001020 mac_addrlow = 0x0cc25000 mac_addrhigh offset = 0x0004 bit31302928272625242322212019181716151413121110 9 8 7 6 5 4 3 2 1 0 padr[47:32] def.00000000000000001111111111111111 bits name description r/w default 31:16 ? reserved. should be cleared. r 0 15:0 padr[47:32] physical address [47:32]. contains the upper 16 bits (47 to 32) of the physical address of the mac. r/w 0xffff mac_addrlow offset = 0x0008 bit31302928272625242322212019181716151413121110 9 8 7 6 5 4 3 2 1 0 padr[31:0] def.11111111111111111111111111111111 bits name description r/w default 31:0 padr[31:0] physical address [31:0]. contains the lower 32 bits (31 to 0) of the phys- ical address of the mac. r/w 0xffffffff
amd alchemy? au1000? processor data book - preliminary 129 ethernet mac controller 30360d 6.5.2.3 multicast address high hash table and low hash table register the 64-bit multicast address hash table is used for group addre ss filtering. for hash filtering, the contents of the destinatio n address in the incoming frame is passed through the crc logic and the upper 6 bits of the crc register are used to index the contents of the hash table. the most significant bit determ ines the register to be used (1 = hi, 0 = low), while the other five bits determine the bit within the register. a value of ?0 0000? selects the bit 0 of the se lected register and a value of ?11111? selects the bit 31 of the selected register. if the corresponding bit in the hash table is '1', then the mult icast frame is accept ed, otherwise it is rejected. if the pass all multicast is set, then all multi-cast fram es are accepted regardless of the multi-cast hash values. the multi cast hash table high register contains the higher 32 bits of the hash table and the multi cast hash table low register contains the lower 32 bits of the hash table. mac_hashhigh offset = 0x000c bit31302928272625242322212019181716151413121110 9 8 7 6 5 4 3 2 1 0 mch[63:32] def.00000000000000000000000000000000 bits name description r/w default 31:0 mch[63:32] multicast address hash table high. these bits map to the upper 32 bits of the 64-bit hash table. r/w 0x00000000 mac_hashlow offset = 0x0010 bit31302928272625242322212019181716151413121110 9 8 7 6 5 4 3 2 1 0 mch[31:0] def.00000000000000000000000000000000 bits name description r/w default 31:0 mch[31:0] multicast address hash table low. these bits map to the lower 32 bits of the 64-bit hash table. r/w 0x00000000
130 amd alchemy? au1000? processor data book - preliminary ethernet mac controller 30360d 6.5.2.4 mii control register the mii address register is used to co ntrol and generate the management cycles to the ex ternal phy controller chip. a write to this register will generate a read/write access on the mii management interface (mdio/mdc) bus to an external phy device. 6.5.2.5 mii data register the mii data register contains the data to be written to the ph y register specified in the mii address register, or it contains the read data from the phy register whose addres s is specified in the mii address register. mac_miictrl offset = 0x0014 bit31302928272625242322212019181716151413121110 9 8 7 6 5 4 3 2 1 0 phyaddr[4:0] miireg[4:0] mw mb def.00000000000000000000000000000000 bits name description r/w default 31:16 ? reserved. should be cleared. r 0 15:11 phyaddr phy address. these bits tell which of the 32 possible phy devices are being accessed. r/w 00000 10:6 miireg mii register. these bits select the desired mii register in the selected phy device. r/w 00000 5:2 ? reserved. should be cleared. r 0 1 mw mii write. 0 operation will be a read (data read is placed in mii data register) 1 operation will be a write (data to be written is taken from mii data register) r/w 0 0 mb mii busy. this bit should read a logic 0 before writing to the mii address and mii data registers. this bit should be reset to 0 when writing to the mii address register. this bit will be set by the mac to signi fy that a read or write access to the external phy is in progress. for a write operation the data register should be kept valid until this bit is cleared by the mac. for a read operation the mii data register is invalid until this bit is cleared by the mac. the mii address register should not be modified until this bit is cleared. the mac clears this bit after the phy access is done. r/w 0 mac_miidata offset = 0x0018 bit31302928272625242322212019181716151413121110 9 8 7 6 5 4 3 2 1 0 miidata[15:0] def.00000000000000000000000000000000 bits name description r/w default 31:16 ? reserved. should be cleared. r 0 15:0 miidata mii data. 16-bit value read from the phy after a mii read operation, or the 16-bit data value to be written to the phy before a mii write operation. r/w 0x0000
amd alchemy? au1000? processor data book - preliminary 131 ethernet mac controller 30360d 6.5.2.6 flow control register this register is used to control the generation and reception of the control (pause command) frames by the mac?s flow control block. a write to this register with the busy bit set to ?1? triggers the flow control block to generate a pause contro l frame. the fields of the contro l frame are selected as specified in the 802.3x specification with the pause time field from this register used in the ?pause time? field of the control fr ame. the busy bit will remain set until the control frame is tran s- mitted. the host has to insure that the busy bit is cleared bef ore writing to the register. the pass control frames bit indi- cates to the mac whether or not to pass the control frame to the host. the flow control enable bit enables the receive portion of the flow control block. mac_flowctrl offset = 0x001c bit31302928272625242322212019181716151413121110 9 8 7 6 5 4 3 2 1 0 pt[15:0] pc fe fb def.00000000000000000000000000000000 bits name description r/w default 31:16 pt pause time. this field will be used in the pause time field in the genera- tion of the pause control frame. r/w 0x0000 15:3 ? reserved. should be cleared. r 0 2 pc pass control frame. 0 the mac decodes the control frames but does not pass the frames to the host. the control frame bit in the receive status (bit 25) is set and the transmitter pause mode signal gives the current status of the transmitter, but the packetfilter bit in the receive status is reset to signal the application to flush the frame. 1 control frames are passed to the host. the mac decodes the control frame (pause) and disables the transmitter for the specified amount of time. the control frame bit in the receive status (bit 25) is set, and the transmitter pause mode signal indicates the current state of the mac transmitter. r/w 0 1 fe flow control enable. 0 the flow control operation in the mac is disabled, and the mac does not decode the frames for control frames. 1 the mac is enabled for flow cont rol operation and it will decode all the incoming frames for control frames. if the mac receives a valid control frame (pause command), it will disable the transmitter for the specified time. this bit is valid only in full duplex mode. r/w 0 0 fb flow control busy status. this bit should read a logic 0 before writing to the flow control register. to initiate a pause control frame the host must set this bit. during a transfer of control frame, this bit remains set to sig- nify that a frame transmission is in progress. after the completion of pause control frame transmission, the mac clears fb. r/w 0
132 amd alchemy? au1000? processor data book - preliminary ethernet mac controller 30360d 6.5.2.7 vlan1 tag register 6.5.2.8 vlan2 tag register mac_vlan1 offset = 0x0020 bit31302928272625242322212019181716151413121110 9 8 7 6 5 4 3 2 1 0 vl1tag[15:0] def.00000000000000001111111111111111 bits name description r/w default 31:16 ? reserved. should be cleared. r 0 15:0 vl1tag vlan 1 tag identifier. this field will be compared with the 13th and 14th bytes of the incoming frame. if a nonzero match occurs the vlan 1 frame bit will be set in the receiver status packet. in addition, the legal length of a frame is increased from 1518 bytes to 1522 bytes. r/w 0xffff mac_vlan2 offset = 0x0024 bit31302928272625242322212019181716151413121110 9 8 7 6 5 4 3 2 1 0 vl2tag[15:0] def.00000000000000001111111111111111 bits name description r/w default 31:16 ? reserved. should be cleared. r 0 15:0 vl2tag vlan 2 tag identifier. this field will be compared with the 13th and 14th bytes of the incoming frame. if a nonzero match occurs the vlan 2 frame bit will be set in the receiver status packet. in addition the legal length of a frame is increased from 1518 bytes to 1538 bytes. r/w 0xffff
amd alchemy? au1000? processor data book - preliminary 133 ethernet mac controller 30360d 6.5.3 mac enable registers each ethernet mac has an identical enable register . both enable registers are located off of the macen_base shown in table 6-21. 6.5.3.1 mac0 and mac1 enable the enable register for each mac contains a bit that enables t he entire block. the block should be disabled if not in use to minimize power consumption. in addition, each enable register contains a toss bit (ts) which prevents frames that do not pass the address filter from being put into memory. the process for bringing the mac out of reset is as follows: 1) enable clocks (ce=1). 2) bring e[2:0] high together with the other bi ts configured as desired (keeping clocks enabled). note: mac clocks must be running before the internal mac registers are accessed. macen_mac0 offset = 0x0000 macen_mac1 offset = 0x0004 bit31302928272625242322212019181716151413121110 9 8 7 6 5 4 3 2 1 0 jp e2 e1 c ts e0 ce def.00000000000000000000000000000000 bits name description r/w default 31:7 ? reserved. should be cleared. w 0 6 jp jumbo packet enable. 0 normal (max packet length = 0x800 bytes) 1 enable jumbo packet (max packet length = 0x2800 bytes) w0 5:4 e[2:1] enable field bits 2 and 1. together with e0, this field resets and enables the mac. 000 reset 111 enable all other combinations are invalid. w00 3 c coherent. 0 memory accesses are marked coherent on system bus 1 memory accesses are marked non coherent on system bus for more information on coherency see section 2.8.2 "sbus coherency model" on page 41. w0 2ts disable toss. 0 only frames passing the address filter are passed to memory. frames which fail length error, crc error, or other non-address filter failures are still passed to memory. frames are not passed to memory if the filter fail bit is set, or the frame is a broadcast frame and br oadcast frames have been dis- abled. in promiscuous mode all frames are passed to memory unless the disable broadcast bit is set whic h prevents broadcast frames from being passed to memory. frames that are not passed to memory are transparent to software? no status or indication informs software. 1 all frames are passed to memory, re gardless of address filter result. w unpred 1 e[0] enable field bit 0. see description for e[2:1]. w 0 0 ce clock enable. 0 clocks disabled to mac 1 clocks enabled to mac w0
134 amd alchemy? au1000? processor data book - preliminary ethernet mac controller 30360d 6.5.4 mac dma registers each mac has four dma buffers for both receive and transmit (4 for rx, 4 for tx). the dma buffers are serviced in a round-robin fashion. each mac has a 32-word fifo for both tr ansmit and receive. the transfer size for the mac dma is 8 words. both the fifo size and transfer size are taken care of automatically by the mac dma and are transparent to the programmer except that all memory buffers must be implemented on a cache line boundary (32 bytes). the mac dma registers can be described as a set of transm it and receive entries off of the mac dma base addresses shown in table 6-21. each mac dma base address contains 8 entries which correspond to 4 transmit buffer entries and 4 receive buffer entries as shown in table 6-23. within each receive entry there are 2 registers implemented as shown in table 6-24. (the third and fourth reserved entries are shown for completeness but are not used.) within each transmit entry, there are three registers implemented as shown in table 6-25. (the fourth reserved entry is shown for completeness but is not used.) table 6-23. mac dma entries offset entry prefix entry name 0x000 tx0 transmit buffer 0 0x010 tx1 transmit buffer 1 0x020 tx2 transmit buffer 2 0x030 tx3 transmit buffer 3 0x100 rx0 receive buffer 0 0x110 rx1 receive buffer 1 0x120 rx2 receive buffer 2 0x130 rx3 receive buffer 3 table 6-24. mac dma receive entry registers offset receive entry register description 0x0 stat status register 0x4 addr address/enable register 0x8 reserved nothing is implemented at this offset. 0xc reserved nothing is implemented at this offset. table 6-25. mac dma transmit entry registers offset transmit entry register description 0x0 stat status register 0x4 addr address/enable register 0x8 len length register 0xc reserved nothing is implemented at this offset.
amd alchemy? au1000? processor data book - preliminary 135 ethernet mac controller 30360d to calculate the address of a specific mac dma buffer all o ffsets should be combined. for example the physical address of the mac1 receive buffer 3 address register is calculated as follows: macdma1_rx3addr = macdma1_base + rx3 + addr = 0x0 1400 4200 + 0x130 + 0x4 = 0x0 1400 4334 another way to look at the dma register addresses is to view them as built off of the base address using an indexed approach to build the address for each unique register within t he block. in other words, each bit (or set of bits) within the address will select a parameter of the dma register (tx/rx, bu ffer number, status/address/length register) until a unique address is formed selecting a single register. to build the address for a unique register the bits shoul d be set according to the definitions in table 6-26. the enumerated dma registers are shown in section a.1 "memory map" on page 271. table 6-26. mac dma block indexed address bit definitions addrbits description 8tx/rx. 0 transmit block 1 receive block 7:6 these bits should be cleared. 5:4 mac dma buffer. 00 buffer 0 01 buffer 1 10 buffer 2 11 buffer 3 3:2 register select. 00 status register 01 address/enable register 10 length register (valid for transmit only) 11 reserved 1:0 these bits should be cleared because the registers are aligned on a word boundary.
136 amd alchemy? au1000? processor data book - preliminary ethernet mac controller 30360d mac dma receive registers there are two receive registers for each dma channel associ ated with each mac: the status register and the address/ enable register. the length register is not applicable to th e receive dma channel, as the length will be determined by the size of the received packet (typically the size of a frame fo r a complete, successful reception). the receive memory buffers should be 0x800 bytes when jumbo packets are not enabled and to 0x2800 when jumbo packets are enabled. this will allow for the worst case maximum reception length. in the naming of the receive registers dummy variables m and n have been inserted into the name to designate mac num- ber ( m ) and buffer number ( n ). 6.5.4.1 receive status this register contains the rece ive packet status bits sent by the mac after rece iving a frame. this register is only valid afte r a receive transaction has been enabled by the host and the done bit has been set by the mac in the address/enable reg- ister to indicate that th e transaction is complete. the mi bit should be checked by software after receiving a frame to verify that the received frame is valid. macdma0_rx n stat offset = 0x0 bit313029282726252423222120191817161514131211109876543210 mi pf ff bf mf uc cf le v2 v1 cr db me ft cs fl rf wt l[13:0] def.xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx bits name description r/w default 31 mi missed frame. 0 the frame is received normally by the application without any latency or error violations 1 indicates that a frame was missed due to an internal fifo overrun. r unpred 30 pf packet filter. 0 indicates that the current frame failed the packet filter. 1 indicates that the current frame passed the packet filter that is imple- mented in the mac. packet filter will indicate failed frame when any of the following conditions happens. a. ff = 0 and frame is not a broadcast or ra is 1 b. frame is broadcast and db is 0 c. frame is not control frame or pc is 1 d. no error status or pb frames is 1 e. unsupported control frame is 0 the application can use this bit to decide whether to keep the packet in the memory or flush the packet from the memory. note that frames with length greater than max ethernet size (1500 bytes- normal, 1518 bytes - vlan1, 1538 bytes - vlan2) will create an error sta- tus thus failing the packet filter. the frames may still be valid with failure only due to frame size. r unpred 29 ff filtering fail. 0 current frame passed address filtering 1 destination address field in the current frame failed the address filter- ing. r unpred 28 bf broadcast frame. 0 destination address is not broadcast. 1 destination address is all 1? s indicating broadcast address. r unpred 27 mf multicast frame. 0 destination address is not multicast. 1 destination address is multic ast (the first bit is 1). r unpred
amd alchemy? au1000? processor data book - preliminary 137 ethernet mac controller 30360d 26 uc unsupported control frame. 0 if the control frame bit is set, th is bit indicates a supported control frame has been received (pause frame). 1 the mac observed an unsupported control frame. this is set when a control frame is received and the opcode field is unsupported, or the length is not equal to minframesize (64 bytes). this bit is set only when the mac is operating in the full-duplex mode. r unpred 25 cf control frame. 0 current frame is not a control frame. 1 current frame is a control frame. this bit is only set when operating in full duplex mode. r unpred 24 le length error. 0 no length error occurred. 1 the current frame length value is in consistent with the total number of bytes received in the current frame. when the number of bytes received in the data field are more than what indicated in the length/ type field, the additional bytes are assumed to be pad bytes and the length error bit is not set. when the number of bytes received in the data field is less than what was indicated in the length/type field, the length error bit is set. this is valid when the frame type is set to ?0? (802.3 frame). this bit is not applicable for frame lengths greater than max ethernet size (1500 bytes- normal, 1518 bytes - vlan1, 1538 bytes - vlan2). r unpred 23 v2 vlan2 id. 0 no match with vlan2 tag. 1 the current frame is tagged with a vlan2 id. the thirteenth and fourteenth bytes of the frame were a nonzero match with the vlan2 tag register. r unpred 22 v1 vlan1 id. 0 no match with vlan1 tag. 1 the current frame is tagged with a vlan1 id. the thirteenth and fourteenth bytes of the frame were a nonzero match with the vlan1 tag register. r unpred 21 cr crc error. 0 no crc error in current frame. 1 crc error occurred in received frame. this bit is not applicable for frame lengths greater than max ethernet size (1500 bytes- normal, 1518 bytes - vlan1, 1538 bytes - vlan2). if a crc check is required it must be done in software. r unpred 20 db dribbling bit. 0 an integer multiple of eight bits was received. 1 a non-integer multiple of eight bits was received. this bit is not valid if either the collision seen bit or runt frame bit is set. if this bit is set and the crc error bit is 0, then the packet is still valid. r unpred 19 me mii error. 0 no mii error. 1 mii error during frame reception. r unpred 18 ft frame type. 0 ieee 802.3 frame. 1 ethernet-type frame (frame length field is greater than max ethernet size (1500 bytes- normal, 1518 bytes - vlan1, 1538 bytes - vlan2). this bit is still applicable when jumbo packets are enabled. this bit is not valid for runt frames of less than 14 bytes. r unpred bits name description r/w default
138 amd alchemy? au1000? processor data book - preliminary ethernet mac controller 30360d 17 cs collision seen. 0 no collision seen during frame reception. 1 the frame was damaged by a collision that occurred after the 64 bytes following the start of frame delimiter (sfd). this is a late colli- sion. r unpred 16 fl frame too long. 0 frame size is less than or equal to max ethernet frame size (1500 bytes- normal, 1518 bytes - vlan1, 1538 bytes - vlan2). 1 frame size is greater than the maximum ethernet specified size (1500 bytes- normal, 1518 bytes - vlan1, 1538 bytes - vlan2). this also applies when jumbo packets are enabled. frame too long is only a length indica tion and does not cause frame trun- cation. r unpred 15 rf runt frame. 0 frame was not damaged in collision window. 1 frame was damaged by a collision or premature termination before the collision window passed. r unpred 14 wt watchdog timeout. 0 frame was received before timeout occurred. 1 the receive watchdog timer expired while receiving the frame. the watchdog timer inside the mac is programmed to be twice the max- framelength. when set, the frame length field is invalid. any time the max frame length is exceeded (0x800 bytes for normal mode, 0x2800 with jumbo packets enabl ed) the wt bit will be set. r unpred 13:0 l[13:0] frame length. indicates length in bytes of the received frame. the host should take into account how the automatic pad stripping (ap) bit in the corresponding mac control register is set, as this will affect how the length field and frame contents should be interpreted. r unpred bits name description r/w default
amd alchemy? au1000? processor data book - preliminary 139 ethernet mac controller 30360d 6.5.4.2 receive buffer address/enable register this register contains the starting addre ss for the receive buffer. the host should en sure that the memory buffer is set up to accommodate the worst case largest frame size to be able to handle all received packets. at worst case the mac will receive 0x800 bytes before aborting a receive in normal mode or 0x2800 bytes when jumbo packets have been enabled in the macen_mac n register. after the transaction has been enabled this register should not be written until the dn bit has been set. the buffer for the dma must be cache line aligned so the lowest 5 bits are not used as part of the address. these bits have been employed as done and enable bits that are exclusive of the address. macdma0_rx n addr offset = 0x4 bit313029282726252423222120191817161514131211109876543210 addr[31:5] cb dn en def.0000000000000000000000000000 xxxx bits name description r/w default 31:5 addr buffer address. upper 27 bits of the starting physical address for the dma buffer. this address must be cache line (32 bytes) aligned so only 27 bits are used. this address must be wr itten for each dma transaction (the address will not remain after the transaction is enabled) r/w 0 4 ? reserved. should be cleared. r 0 3:2 cb current buffer. current dma receive buffer r unpred 1 dn transaction done. this bit will be se t by hardware to indicate that the receive transaction has been completed and that the receive packet status is valid. if the respective mac dma interrupt is enabled (see section 5.0 "interrupt controller" on page 81), an interrupt wi ll be generated when this bit is set. done bits for all tx and rx buffers are or?ed together for this interrupt so a high level interrupt should be used. this bit must be cleared explicitly by software after checking for done. this will also clear the interrupt. r/w unpred 0 en mac dma enable. when set, this bit enables a dma receive transaction to the memory location designated in addr. r/w unpred
140 amd alchemy? au1000? processor data book - preliminary ethernet mac controller 30360d mac dma transmit registers there are three transmit registers, including the status regist er, the address/enable register, and the length register. in the naming of the receive registers dummy variables m and n have been inserted into the name to designate mac number ( m ) and buffer number ( n ). 6.5.4.3 transmit packet status register this register contains the transmit packet status bits sent by the mac after transmitting a frame. this register is valid after a transmit transaction has been enabled by the host and the done bit has been set by the mac in the address/enable reg- ister to signify that the transmit transaction is complete. if either pr (bit 31) or fa (bit 0) is set then the fram e was not sent successfully and the application should resend the frame. macdma m _tx n stat offset = 0x0 bit31302928272625242322212019181716151413121110 9 8 7 6 5 4 3 2 1 0 pr cc lo df ur ec lc ed ls nc jt fa def.xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx bits name description r/w default 31 pr packet retry. 0 transmission of current packet is complete. 1 the application has to restart the transmission of the frame (packet) when this bit is set to ?1?. the successful/unsuccessful completion of the frame?s transmission is indicated by the frame aborted bit (bit 0). r unpred 30:14 ? these bits are reserved. r unpred 13:10 cc collision count. this 4-bit count in dicates the number of collisions that occurred before the frame was transmitted. this bit is not valid when the excessive collisions bit is set. this bit is valid only when the ma c is operating in half-duplex mode. r unpred 9 lo late collision observed 0 no late collision observed during transmission. 1 indicates that the mac observed a late collision (collision after 64 bytes into transmission of frame), but retransmitted the frame in the next retransmission attempt. this bit will be set when the late colli- sion bit is set. this bit is valid only when the ma c is operating in half-duplex mode. r unpred 8 df deferred. 0 transmitter did not defer when transmitting. 1 the transmitter had to defer whil e ready to transmit a frame. this bit is valid only when operating in half-duplex mode. r unpred 7 ur under run. 0 no data under run. 1 the transmitter aborted the message because of data under run dur- ing the frame?s transmission. r unpred 6 ec excessive collisions. 0 transmission did not abort due to excessive collisions. 1 transmission aborted after 16 success ive collisions. if the disable retry bit is set, this bit is set a fter the first collision and the transmis- sion of the frame will be aborted. this bit is valid only when operating in half-duplex mode. r unpred 5 lc late collision. 0 no late collision. 1 transmission was aborted due to collis ion occurring after the collision window of 64 bytes. this bit is not valid if under run error is set. this bit is valid only when operating in half-duplex mode. r unpred
amd alchemy? au1000? processor data book - preliminary 141 ethernet mac controller 30360d 4 ed excessive deferral. 0 no excessive deferral. 1 transmission has ended because of excessive deferral of over 24,288 bit times during the transmission, if the defer bit is set high in the control register. this bit is valid only when operating in half-duplex mode. r unpred 3 ls loss of carrier. 0 no loss of carrier. 1 the loss of carrier occurred during the frame's transmission (i.e., the crs input was inactive for one or more bit times when the frame is being transmitted). this bit is valid only when operating in half-duplex mode. r unpred 2nc no carrier. 0 carrier present. 1 the carrier signal from the transce iver was not present during trans- mission. this bit is valid only when operating in half-duplex mode. r unpred 1 jt jabber timeout. 0 no jabber timeout. 1 the mac transmitter has been acti ve for an abnormally long time (twice the ethernet maxframelength size). r unpred 0 fa frame aborted. 0 current frame was successfully transmitted. 1 the transmission of the current frame has been aborted by the mac because of one or more of the following conditions: jabber timeout (bit 1) no carrier (bit 2) loss of carrier (bit 3) excessive deferral (bit 4) late collision (bit 5) retry count exceeds the attempt limit (bit 6). data under run (bit 7) r unpred bits name description r/w default
142 amd alchemy? au1000? processor data book - preliminary ethernet mac controller 30360d 6.5.4.4 transmit buffer address/enable register this register contains the starting addre ss for the transmit memory buffer. the mac dma transfers the number of bytes designated in the length register. the buffer for the dma must be cache line aligned so the lowest 5 bits are not used as part of the address. these bits have been employed as done and enable bits and are exclusive of the address. 6.5.4.5 transmit buff er length register this register contains the length of the memory buffer in bytes to be transmitted. macdma m _tx n addr offset = 0x4 bit313029282726252423222120191817161514131211109876543210 addr[31:5] cb dn en def.0000000000000000000000000000xxx0 bits name description r/w default 31:5 addr buffer address. upper 27 bits of the starting physical address for the dma buffer?but not including the most si gnificant nibble address bits 35:32. this address must be cache line (32 by tes) aligned so only 27 bits are used. note: this address must be written for each dma transaction (the address will not remain after the transaction is enabled). r/w 0 4 ? reserved. should be cleared. r 0 3:2 cb current buffer. current dma transmit buffer r unpred 1 dn transaction done. this bit will be se t by hardware to indicate that the transmit transaction has been completed and that the transmit packet sta- tus is valid. if the respective mac dma interrupt is enabled (see section 5.0 "interrupt controller" on page 81), an interrupt wi ll be generated when this bit is set. done bits for all tx and rx buffers are or?ed together for this interrupt so a high level interrupt should be used. this bit must be cleared explicitly by software after checking for done. this will also clear the interrupt. r/w unpred 0 en mac dma enable. when set, this bit enables a dma transmit transaction from the memory location designated in addr. r/w macdma m _tx n len offset = 0x8 bit313029282726252423222120191817161514131211109876543210 len[13:0] def.00000000000000000000000000000000 bits name description r/w default 31:14 ? reserved. should be cleared. r 0 13:0 len buffer length. this field sets the length of the memory buffer (in bytes). when the normal bit is set, the length can only be up to 0x800 bytes. when the jumbo packets are enabled in the enable register, the length can be set up to 0x2800 bytes. r/w 0
amd alchemy? au1000? processor data book - preliminary 143 ethernet mac controller 30360d 6.5.5 hardware connections table 6-27 shows the signals associated with the two ethernet mac mii interfaces. table 6-27. ethernet signals signal input/output description ethernet controller 0 (mac0) n0txclk i continuous clock input for synchronization of transmit data. 25 mhz when operating at 100-mbps and 2.5 mhz when operating at 10 mbps. n0txen o indicates that the data nibble on n0txd[3:0] is valid. n0txd[3:0] o nibble wide data bus synchronous to n0txclk. for each n0txclk period in which n0txen is asserted, txd[3:0] will have the data to be accepted by the phy. while n0txen is de-asserted the data pr esented on txd[3:0] should be ignored. n0rxclk i continuous clock that provides the timing reference for the data transfer from the phy to the mac. n0rxclk is sourced by the phy. the n0rxclk shall have a frequency equal to 25% of the data rate of the received signal data stream (typically 25 mhz at 100 mb/s and 2.5 mhz at 10 mb/s). n0rxdv i active high. indicates that a receive frame is in process and that the data on n0rxd[3:0] is valid. n0rxd[3:0] i rxd[3:0] is a nibble wide data bus driven by the phy to the mac synchronous with n0rxclk. for each n0rxclk period in wh ich n0rxdv is asserted, rxd[3:0] will transfer four bits of recovered data from the phy to the mac. while n0rxdv is de- asserted, rxd[3:0] will have no effect on the mac. n0crs i n0crs shall be asserted by the phy when either transmit or receive medium is non idle. n0crs shall be deasserted by the phy when both the transmit and receive medium are idle. n0crs is an asynchronous input. n0col i n0col shall be asserted by the phy upon detection of a collision on the medium, and shall remain asserted while the collision condition persists. n0col is an asyn- chronous input. the n0col signal is ignored by the mac when operating in the full duplex mode. n0mdc o n0mdc is sourced by the mac to the phy as the timing reference for transfer of information on the n0mdio signal. n0mdc is an aperiodic signal that has no maxi- mum high or low times. the n0mdc frequency is fixed at system bus clock divided by 160. n0mdio io n0mdio is the bidirectional data signal between the mac and the phy that is clocked by n0mdc. ethernet controller 1 (mac1) n1txclk i continuous clock input for synchronization of transmit data. 25 mhz when operating at 100-mbps and 2.5 mhz when operating at 10 mbps. n1txen o indicates that the data nibble on n1txd[3:0] is valid. muxed with gpio[24]. n1txen is the default signal coming out of hardware reset, runtime reset, and sleep. n1txd[3:0] o nibble wide data bus synchronous to n1txclk. for each n1txclk period in which n1txen is asserted, txd[3:0] will have the data to be accepted by the phy. while n1txen is de-asserted the data pr esented on txd[3:0] should be ignored. muxed with gpio[28:25]. n1txd[3:0] are the default signals coming out of hard- ware reset, runtime reset, and sleep. n1rxclk i continuous clock that provides the timing reference for the data transfer from the phy to the mac. n1rxclk is sourced by the phy. the n1rxclk shall have a frequency equal to 25% of the data rate of the received signal data stream (typically 25 mhz at 100 mbps and 2.5 mhz at 10 mbps)
144 amd alchemy? au1000? processor data book - preliminary ethernet mac controller 30360d mac1 shares its pins with gp io[28:24]; these pins must be assigned to ma c1 in order to use mac1. see section 7.3 "general purpose i/o and pin functionality" on page 183 for more information. n1rxdv i indicates that a receive frame is in pr ocess and that the data on n1rxd[3:0] is valid. n1rxd[3:0] i rxd[3:0] is a nibble wide data bus driven by the phy to the mac synchronous with n1rxclk. for each n1rxclk period in wh ich n1rxdv is asserted, rxd[3:0] will transfer four bits of recovered data from the phy to the mac. while n1rxdv is de- asserted, rxd[3:0] will have no effect on the mac. n1crs i n1crs shall be asserted by the phy when either transmit or receive medium is non idle. n1crs shall be deasserted by the phy when both the transmit and receive medium are idle. n1crs is an isochronous input. n1col i n1col shall be asserted by the phy upon detection of a collision on the medium, and shall remain asserted while the collision condition persists. n1col is an asyn- chronous input. the n1col signal is ignored by the mac when operating in the full duplex mode. n1mdc o n1mdc is sourced by the mac to the phy as the timing reference for transfer of information on the n1mdio signal. n1mdc is an aperiodic signal that has no maxi- mum high or low times. the n1mdc frequency is fixed at system bus clock divided by 160. n1mdio io n1mdio is the bidirectional data signal between the mac and the phy that is clocked by n1mdc. table 6-27. ethernet signals (continued) signal input/output description
amd alchemy? au1000? processor data book - preliminary 145 ethernet mac controller 30360d 6.5.6 programming considerations the ethernet mac is designed such that the application could use a pool of memory buffers for both the transmit and receive functions. the lowest level device driver would respond to the mac dma interrupt and swap out the filled dma buffers for those that are empty for the receive case. for the transmit case the driver should provide ready to transmit buffers to the dma while reclaiming empty buffers. four transmit and receive dma buffers are allocated for each mac to allow for latency to service the lowest level mac dma interrupt. at the next level in software the device driver can parse the valid data out of the frame for receive, or build the frame for transmit. the number of memory buffers needed in the pool will depend on how fast the parsing can occur for worst case receive bursts, and any minimum transmit latency requirements. from this level the application or protocol st ack can take the data and apply it as needed. 6.5.6.1 initialization this section demonstrates the functional requirements for getting the mac running. this assumes that the programmer has already performed the au1000 bringup. 1) interrupt controller - a high level interrupt should be used as the interrupt is triggered with an or?ing of the dn (done) bits. 2) dma controller setup 3) mac registers - it is the system designer?s responsibility to set up addresses. 4) memory - depending on how the system is built, there coul d be a pool of memory buffers which can be used for pars- ing and building of frames. individual buffers would be sw apped in and out of the 4 active receive and transmit dma buffers as needed. this strategy would require some sort of minimal memory management within the ethernet driver to insure chronology of ethernet frames. the following is a transmit example in a basic form. typically this would be split between an interrupt handler and another higher layer. 1) construct frame 2) set length in macdma m _tx n len register 3) set address of memory buffer and enable transmit. during this time the physical memory buffer and address and length registers should not be disrupted or transmit contents will be undefined. 4) wait for done. this can be done by waiting for the interrupt handler or polling the done signal in the macdma m _tx n addr register. 5) read status. its validity is signaled by the reception of the done signal. the following is a basic receive example: 1) enable all receive buffers with four different memory buffer addresses. 2) wait for interrupt. conversely the done bit could be polle d. during this time the physical memory buffer and address registers should not be disrupted or receive contents will be undefined. 3) replace all full buffers with empty memory buffers. 4) read status for full buffers. 5) parse frames.
146 amd alchemy? au1000? processor data book - preliminary i2s controller 30360d 6.6 i 2 s controller the au1000 contains an i 2 s controller capable of interfacing with a codec or a discreet dac and adc. the i 2 s interface works in two different modes: unidirectional data mode and bidirectional data mode. in unidirectional data mode the i2sdi signal is not used. in th is mode the i2sdio signal can be configured as an input or an output and can be used with either an adc or a dac at any one time. in bidirectional mode the i2sdio signal is configured as an output and used in conjunction with i2sdi to interface the port to a codec or discreet adc and dac. the port will only support one input at any one time. in other words, i2sdio can not be enabled as an input at the same time i2sdi is being used. 6.6.1 i 2 s register descriptions the i 2 s interface is controlled by a register block whos e physical base address is shown in table 6-28. the i 2 s register block consists of 3 registers as shown in table 6-29. 6.6.1.1 i 2 s data the i 2 s data register is the input to the transmit fifo when written to and the output from the receive fifo when read from. each fifo is 12 words deep. care should be taken to monitor the status register to insure that there is room for data for a write or data in the fifo for a read transaction. the fifo is for both the left and the right channels. for this reason data should be read fr om and written to the fifo in pairs. the programmer should insure that data is written to th e fifo corresponding to how the justification, initial channel, and size is configured. if the sample si ze being written or read is different th an the size being configured, the programmer should justify the data accordingly. table 6-28. i 2 s base address name physical base address kseg1 base address i2s_base 0x0_1100_0000 0x_b100_0000 table 6-29. i 2 s interface register block offset register name type description 0x0000 i2s_data r/w input and output from data fifos 0x0004 i2s_config r/w configur ation and status register 0x0008 i2s_enable r/w allows port to be enabled and disabled i2s_data - tx/rx data offset = 0x0000 bit 313029282726252423222120191817161514131211109876543210 data[23:0] def. 00000000000000000000000000000000 bits name description r/w default 31:24 ? reserved. should be cleared. r 0 23:0 data data word up to 24 bits. when written, this field is the transmit data. when read, this field is the receive data. r/w
amd alchemy? au1000? processor data book - preliminary 147 i2s controller 30360d 6.6.1.2 configuration and status register the i 2 s interface configuration and status register contains stat us bits for the transmit and receive fifos, and configura- tion bits for the interface. i2s_config - configuration and status offset = 0x0004 bit 313029282726252423222120191817161514131211109876543210 xu xo ru ro tr te tf rr re rf ick pd lb ic fm tn rn sz def. 00000000000000000000000000000000 bits name description r/w default 31:26 ? reserved. should be cleared. r 0 25 xu transmit fifo underflow status. 0 no underflow. 1 underflow error condition. this sticky bit is cleared by writing a ?0 ? to it. because this register is also used for configuration, mask this bit with a ?1? to preserve its value if needed. r/w 0 24 xo transmit fifo overflow status. 0 no overflow. 1 overflow error condition. this sticky bit is cleared by writing a ?0 ? to it. because this register is also used for configuration, mask this bit with a ?1? to preserve its value if needed. r/w 0 23 ru receive fifo underflow status. 0 no underflow. 1 underflow error condition. this sticky bit is cleared by writing a ?0 ? to it. because this register is also used for configuration, mask this bit with a ?1? to preserve its value if needed. r/w 0 22 ro receive fifo overflow status. 0 no overflow. 1 overflow error condition. this sticky bit is cleared by writing a ?0 ? to it. because this register is also used for configuration, mask this bit with a ?1? to preserve its value if needed. r/w 0 21 tr transmit request. this bit indicates th at the transmit fifo has at least 4 samples of space to accommodate a burst write. r0 20 te transmit empty. this bit indicate s that the transmit fifo is empty. r 0 19 tf transmit full. this bit indica tes the transmit fifo is full. r 0 18 rr receive request. this bit indicates t hat the receive fifo has at least 4 samples in it to accommodate a burst read. r0 17 re receive empty. this bit indicates that the receive fifo is empty. r 0 16 rf receive full. this bit indicates that the receive fifo is full. r 0 15:13 ? reserved. should be cleared. r 0 12 ick invert clock. 0 data is valid on falling edge. 1 data is valid on rising edge. r/w 0
148 amd alchemy? au1000? processor data book - preliminary i2s controller 30360d 11 pd pin direction. configures th e direction of the i2sdio signal. 0 i2sdio is an output?for unidirectio nal or bidirectional operation. for the unidirectional transmit case, do not use i2sdi. note also in this case that the gpio[8] function (which is muxed with i2sdi) can be used only as an output unless the i 2 s receive function is disabled (rn=0). 1 i2sdio is an input?for unidirect ional operation only. do not use i2sdi. note also in this unidirectional receive case that the gpio[8] function (which is muxed with i2sdi) can be used only as an output . r/w 0 10 lb loopback. when set this bit will enable a loop back mode where data com- ing on the input will be presented on the output. r/w 0 9 ic initial channel. 0 the left sub channel is the first presented. this means that data will not be presented until the word clock is the correct polarity for left as described in format. 1 the right sub channel is the first pr esented. this means that data will not be presented until the word clock is the correct polarity for right (as described in the format section of this table). r/w 0 8:7 fm format. the following formats are supported: 00 i 2 s mode. in this mode the first bit of a sample word will be presented after one i2sclk delay from the transition of i2sword. the left sample data will be presented when th e word clock is low. the data is presented msb first. 01 left justified mode. in this mode the first bit of a sample word will be presented on the first i2sclk after an i2sword transition. the left sample data will be presented when the word clock is high. the data is presented msb first. 10 right justified mode. in this mode th e first bit of a sample word will be presented on the first i2sclk after an i2sword transition. the left sample data will be presented when the word clock is high. the data is presented lsb first. 11 reserved. r/w 00 6 tn transmit enable. this will enable the transmit fifo and must be enabled if the output is being used. 0 disable transmit fifo. 1 enable transmit fifo. r/w 0 5 rn receive enable. this will enable the receive fifo and must be enabled if either of the inputs are being used. 0 disable receive fifo. 1 enable receive fifo. r/w 1 4:0 sz size. these bits will set the size of the sample word. the following combi- nations are valid: 01000 8-bit words 10000 16-bit words 10010 18-bit words 10100 20-bit words 11000 24-bit words if using dma it is important that memo ry is packed consistently with the transfer width programmed for th e dma channel and the size field. r/w 10010 bits name description r/w default
amd alchemy? au1000? processor data book - preliminary 149 i2s controller 30360d 6.6.1.3 i 2 s enable the i 2 s block control register is used to enable clocks to and reset the entire i 2 s block. the suggested power on reset is as follows: 1) set both ce and d. 2) clear d for to enable the peripheral. 6.6.2 hardware considerations table 6-30 shows the signals associated with this port. i2s_enable - i 2 s block control offset = 0x0008 bit 313029282726252423222120191817161514131211109876543210 d ce def. 00000000000000000000000000000010 bits name description r/w default 31:2 ? reserved. should be cleared. w 0 1d disable. setting this bit will disable the i 2 s block. after enabling the clock with ce, this bit should be cleared for normal operation. w1 0ce clock enable. this bit should be set to enable the clock driving the i 2 s block. it can cleared to disable the clock for power considerations. w0 table 6-30. i 2 s signals signal input/output description i2sclk o serial bit clock. muxed with gpio[30]. i2sclk is the defaul t signal coming out of hardware reset, runtime reset, and sleep. i2sword o word clock typically configured to the sampling frequency (fs). muxed with gpio[31]. i2sword is the def ault signal coming out of hardware reset, runtime reset, and sleep. i2sdi i serial data input sampled on the rising edge of i2sclk. note that i2sdi is used as the input for bidirectional operation only, in which case it is used in conjunction with i2sdio as the output ( i2s_config [pd]=0). muxed with gpio[8]. gpio[8] is the defau lt signal coming out of hardware reset, runtime reset, and sleep. system note : for systems that use the i 2 s interface for unidirectional operation (i2sdi not used), the gpio[8] function is available but with the following restric- tions: when i2sdio is configured as an input , gpio[8] can be used only as an output. when i2sdio is configured as an output , the i 2 s receive function must be dis- abled if gpio[8] is to be used as an input. i2sdio io configurable as input or output. as input, data should be presented on rising edge. as output, data is valid on the rising edge. muxed with gpio[29]. i2sdio is the default signal coming out of hardware reset, runtime reset, and sleep. extclk n o this is the system audio clock and typically is programmed to 256 * fs ( where fs is the sampling frequency for the system). the system audio clock should be taken from extclk0 or extclk1 because these signals are synchronous to i2sclk and i2sword. these clocks are prog rammed individually; see section 7.1 "clocks" on page 168.
150 amd alchemy? au1000? processor data book - preliminary i2s controller 30360d for changing pin functionality, see the sys_pinfunc register description in section 7.3 "general purpose i/o and pin func- tionality" on page 183. 6.6.3 programming considerations it is the programmer?s responsibility to set up dma channels, and the clocks (i2sclk and the extclk n ) to be used with the system. the i2sword clock, which is typically equal to the sampling fr equency, is a function of the word width and the i2sclk fre- quency. i2sclk and extclk n are programmable as described in sect ion 7.1 "clocks" on page 168. the extclk n sig- nals are the external clocks available on the pins shared with gpio[2] and gpio[3].
amd alchemy? au1000? processor data book - preliminary 151 uart interfaces 30360d 6.7 uart interfaces the au1000 contains four uart interfaces. each uart has the following features: 5 - 8 data bits 1 - 2 stop bits even, odd, mark, or no parity 16 byte transmit and receive fifos interrupts for receive fifo full, half full, and not empty interrupts for transmit fifo empty false start bit detection full modem control signals on uart3 capable of speeds up to 1.5 mbps to enable connections wit h bluetooth and other periphera ls through a uart interface similar to personal computer industry standard 16550 uart 6.7.1 programming model each uart is controlled by a register block. table 6- 31 lists the base address for each uart register block. uart0 and uart3 are capable of being used with dma. see se ction 4.0 "dma controller" on page 73 for more informa- tion. 6.7.2 uart registers each register block contains the registers listed in table 6-32. table 6-31. uart register base addresses name physical base address kseg1 base address uart0_base 0x0_1110_0000 0x_b110_0000 uart1_base 0x0_1120_0000 0x_b120_0000 uart2_base 0x0_1130_0000 0x_b130_0000 uart3_base 0x0_1140_0000 0x_b140_0000 table 6-32. uart registers offset register name description 0x0000 uart_rxdata received data fifo 0x0004 uart_txdata transmit data fifo 0x0008 uart_inten interrupt enable register 0x000c uart_intcause pending interrupt cause register 0x0010 uart_fifoctrl fifo control register 0x0014 uart_linectrl line control register 0x0018 uart_mdmctrl modem line control register (uart3 only) 0x001c uart_linestat line status register 0x0020 uart_mdmstat modem line status register (uart3 only) 0x0024 uart_autoflow automatic hardware flow control (uart3 only) 0x0028 uart_clkdiv baud rate clock divider 0x0100 uart_enable module enable register
152 amd alchemy? au1000? processor data book - preliminary uart interfaces 30360d 6.7.3 received data fifo the uart_rxdata register contains the next entry in the received data fifo. this register is read only. 6.7.4 transmit data fifo the uart_txdata register provides access to the transmit data fifo. this register is write only. 6.7.5 interrupt enable register the uart_inten register contains bits which enable in terrupts under certain operational conditions. uart_rxdata - received data fifo offset = 0x0000 bit313029282726252423222120191817161514131211109876543210 rxdata def.00000000000000000000000000000000 bits name description r/w default 31:8 ? reserved. should be cleared. r 0 7:0 rxdata receive data r 0 uart_txdata - transmit data fifo offset = 0x0004 bit313029282726252423222120191817161514131211109876543210 txdata def.00000000000000000000000000000000 bits name description r/w default 31:8 ? reserved, should be cleared. r 0 7:0 txdata transmit data r 0 uart_inten - interrupt enable register offset = 0x0008 bit313029282726252423222120191817161514131211109876543210 mie lie tie rie def.00000000000000000000000000000000 bits name description r/w default 31:4 ? reserved. should be cleared. r 0 3 mie modem status interrupt enable (uart3 only). when the mie bit is set an interrupt is generated when changes occur in the state of the optional modem control signals available with uart3. system note : for systems that use the uart3 interface but do not use the optional modem control signals ( sys_pinfunc [ur3]=0), the modem status interrupts must be disabled (mie=0) to avoid false uart3 interrupts when using gpio[9], gpio[10], gpio[ 11], or gpio[12] as a general-pur- pose system input. r/w 0 2 lie line status interrupt enable. when the lie bit is set an interrupt is gener- ated when errors (overrun, framing, stop bits) or break conditions occur. r/w 0 1 tie transmit interrupt enable. when the tie bit is set an interrupt is generated when the transmit fifo is not full. r/w 0 0 rie receive interrupt enable. when the rie bit is set the uart will generate an interrupt on received data ready ( dr bit in the uart_linestat register) or a character time out. r/w 0
amd alchemy? au1000? processor data book - preliminary 153 uart interfaces 30360d 6.7.6 interrupt cause register the uart_intcause register contains information about the cause of the current interrupt. table 6-33 contains information about the interrupt cause encoding. uart_intcause - interrupt cause register offset = 0x000c bit313029282726252423222120191817161514131211109876543210 iid ip def.00000000000000000000000000000001 bits name description r/w default 31:4 ? reserved. should be cleared. r 0 3:1 iid interrupt identifier. the iid field identifies the highest priority current inter- rupt condition. table 6-33 lists the pr iorities and encodings of each inter- rupt condition. r0 0 ip no interrupt pending. 0 an interrupt is pending. 1 no interrupts are pending. r1 table 6-33. interrupt cause encoding iid priority type source 0 5 (lowest) modem status dd, tri, dr or dc of uart_mdmstat 1 4 transmit buffer available tt of uart_linestat 2 3 receive data available the receive fifo having greater than rft (of uart_fifoctrl ) bytes in it if fifos are enabled. dr of uart_linestat if fifos are disabled. 3 1 (highest) receive line status oe, pe, fe, bi in uart_linestat register 4reserved 5reserved 6 2 character time out character has been in receive fifo for 0x300 uart clocks (set by uart_clkdiv ) 7reserved
154 amd alchemy? au1000? processor data book - preliminary uart interfaces 30360d 6.7.7 fifo control register the uart_fifoctrl register provides control of character buffering options. uart_fifoctrl - fifo control register offset = 0x0010 bit313029282726252423222120191817161514131211109876543210 rft tft ms tr rr fe def.00000000000000000000000000000000 bits name description r/w default 31:8 ? reserved. should be cleared. r 0 7:6 rft receive fifo threshold. a receive threshold interrupt is generated when the number of characters in the rece iver fifo is great er than or equal to the trigger level listed below: 00 trigger depth = 1 01 trigger depth = 4 10 trigger depth = 8 11 trigger depth = 14 if using dma it is important that the receive fifo threshold and transmit fifo threshold are the same and prog rammed consistently with the trans- fer size for the dma channel being used. see section 4.0 "dma control- ler" on page 73 for more information. r/w 0 5:4 tft transmit fifo threshold. a transmi t threshold interrupt is generated if the number of valid characters contained in the transmit fifo is less than or equal to the trigger depth. the encoding of trigger depth for each value of tft is shown below: 00 trigger depth = 0 01 trigger depth = 4 10 trigger depth = 8 11 trigger depth = 12 if using dma it is important that the receive fifo threshold and transmit fifo threshold are the same and prog rammed consistently with the trans- fer size for the dma channel being used. see section 4.0 "dma control- ler" on page 73 for more information. r/w 0 3 ms mode select. if the ms bit is clear interrupts are generated by the receiver when any data is available and by the transmitter when there is no data to transmit. setting the ms bit causes interrupts to be generated based on fifo threshold levels. r/w 0 2 tr transmitter reset. writing a one to t he tr bit will clear the transmit fifo and reset the transmitter. the transmit shift register is not cleared. r/w 0 1 rr receiver reset. writing a one to the rr bit will clear the receiver fifo and reset the receiver. the receiver shift register is not cleared. r/w 0 0 fe fifo enable. the fe bit enables the 16 byte fifos on transmit and receive. when the fe bit is clear both fifos will have an effective depth of 1 byte. r/w 0
amd alchemy? au1000? processor data book - preliminary 155 uart interfaces 30360d 6.7.8 line control register the uart_linectrl register provides control over the data format and parity options. 6.7.9 modem control register the uart_mdmctrl register allows the state of the output modem control signals to be set. the external modem signals are only available on uart3. uart_linectrl - line control register offset = 0x0014 bit313029282726252423222120191817161514131211109876543210 sb par pe st wls def.00000000000000000000000000000000 bits name description r/w default 31:7 ? reserved. should be cleared. r 0 6 sb send break. setting the sb bit will forc e the transmitter output to zero. r/w 0 5:4 par parity select. selects the parity encoding for the transmitter and receiver. 00 odd parity 01 even parity 10 mark parity 11 zero parity r/w 0 3 pe parity enable. if the pe bit is clear parity will not be sent or expected. if the pe bit is set parity is select ed according to the par field. r/w 0 2 st stop bits. if the st bit is clear one stop bit is sent and expected. setting the st bit selects 1.5 stop bits for 5 bit characters and 2 stop bits for all other character lengths. r/w 0 1:0 wls word length select. the wls field selects the number of data bits in each character. the number of bits is wls+5. r/w 0 uart_mdmctrl - modem control register offset = 0x0018 bit313029282726252423222120191817161514131211109876543210 lb i1 i0 rt dt def.00000000000000000000000000000000 bits name description r/w default 31:5 ? reserved. should be cleared. r 0 4 lb loop back. 0 no loopback (normal operation) 1 enable loopback for self-test. establish the internal connections shown below: output signal looped back to txd rxd dtr dsr rts cts i0 rin i1 dcd r/w 0 3 i1 internal line 1 state. when the i1 bit is set the internal i1 line for this port is driven low. this can be used in loopback mode. r/w 0 2 i0 internal line 0 state. when the i0 bit is set the external i0 line for this port is driven low.this can be used in loopback mode. r/w 0 1 rt request to send. when the rt bit is set the external rts line for this port is driven low. note: this bit has no effect if uart_autoflow [ae] is set. r/w 0 0 dt data terminal ready. when the dt bit is set the external dtr line for this port is driven low. r/w 0
156 amd alchemy? au1000? processor data book - preliminary uart interfaces 30360d 6.7.10 line status register the uart_linestat register reflects the state of the interface. bits in this register are set when the listed condition and cleared when this register is read. uart_linestat - line status register offset = 0x001c bit313029282726252423222120191817161514131211109876543210 rf te tt bi fe pe oe dr def.00000000000000000000000000000000 bits name description r/w default 31:8 ? reserved. should be cleared. r 0 7 rf receiver fifo contains error. this bit is set when one of the characters in the receive fifo contains a parity erro r, framing error, or break indication. r0 6 te transmit shift register empty. this bit is set when the transmit shift regis- ter is empty and there are no more characters in the fifo. r0 5 tt transmit threshold. this bit is se t when the transmitter fifo depth is less than or equal to the value of the tft field in the fifo control register. when fifos are not enabled this bit is set when the transmitter data regis- ter is empty r0 4 bi break indication. this bit is set if a break is received. when a break is detected a single zero character is received. the bi bit is valid when the zero character is at the top of the receive fifo. this bit must be cleared with a read to uart_linestat before more characters are received. r0 3 fe framing error. the fe bit is set when a valid stop bit is not detected. this bit reflects the state of the character at the top of the receive fifo. the fe bit is cleared by a read to uart_linestat . r0 2 pe parity error. the pe bit is set when the received character at the top of the fifo contains a parity error. th is bit is cleared by reading uart_linestat . r0 1 oe overrun error. the oe bit is set when a receiver overrun occurs. this bit is cleared when uart_linestat is read. r0 0 dr data ready. the dr bit is set when the receive fifo contains valid char- acters. r0
amd alchemy? au1000? processor data book - preliminary 157 uart interfaces 30360d 6.7.11 modem status register the uart_mdmstat register reflects the stat e of the external modem signals. reading this register will clear any delta indi- cations and the corresponding interrupt. the external mo dem signals are optional and are present only on uart3. 6.7.12 automatic hardware flow control register the uart_autoflow register controls automatic hardware flow control using modem control signals cts and rts. upon enabling this mode, internal logic controls the output signal rts based upon the data register state and threshold levels. the internal logic asserts rts (low) to request data until the internal receive fifo reaches its preset threshold. in this mode rts cannot be controlled with the uart_mdmctrl [rt] bit. the input signal cts c ontrols the transmission of data by loading the transmit shift register from the data register only while cts is asserted (low). once the transmit shift register i s loaded with data, it sends the entire character regardless of the cts signal state. uart3_mdmstat - modem status register offset = 0x0020 bit313029282726252423222120191817161514131211109876543210 cd ri ds ct dd tri dr dc def.00000000000000000000000000000000 bits name description r/w default 31:8 ? reserved, should be cleared. r 0 7 cd data carrier detect. the cd bit reflects the status of the external dcd pin. r 0 6 ri ring indication. the ri bit reflects the status of the external ri pin. r 0 5 ds data set ready. the ds bit reflects the status of the external dsr pin. r 0 4 ct clear to send. the ct bit reflects the status of the external cts pin. r 0 3 dd delta dcd. the dd bit is set when a change occurs in the state of the external dcd pin. r0 2 tri tri - terminate ring indication. the tri bit is set when a positive edge occurs in the state of the external ri pin. r0 1 dr delta dsr. the dr bit is set when a change occurs in the state of the external dsr pin. r0 0 dc delta cts. the dc bit is set when a change occurs in the state of the external cts pin. r0 uart_autoflow - automatic hardware flow control register offset = 0x0024 bit313029282726252423222120191817161514131211109876543210 ae def.00000000000000000000000000000000 bits name description r/w default 31:1 ? reserved. should be cleared. r 0 0 ae autoflow enable. setting this bit enables automatic hardware flow control on uart3. enabling this mode overrides software control of the signals. r/w 0
158 amd alchemy? au1000? processor data book - preliminary uart interfaces 30360d 6.7.13 clock divider register the uart_clkdiv contains the divider used to generate the baud rate cloc k. the input to the uart clock divider is the inter- nal peripheral bus clock. the actual baud rate of the interface is as follows: baud rate = cpu / (sd * 2 * clkdiv * 16) cpu = cpu clock sd = system bus divider (see section 7.4 "power management" on page 188 information on changing sd.) 6.7.14 uart enable the uart_enable register controls reset and clock enable to the uart the correct routine for bringing the usb device out of reset is as follows: 1) set the ce bit to enable clocks. 2) set the e bit to enable the peripheral. uart_clkdiv - clock divider register offset = 0x0028 bit313029282726252423222120191817161514131211109876543210 clkdiv def.00000000000000000000000000000001 uart_enable - uart enable register offset = 0x0100 bit313029282726252423222120191817161514131211109876543210 ece def.00000000000000000000000000000000 bits name description r/w default 31:2 ? reserved. should be cleared. r 0 1 e enable. when the e bit is clear the entire module is held in reset. after enabling clocks, this bit should be set to enable normal operation. r/w 0 0 ce clock enable. when the ce bit is cl ear the module clock source is inhib- ited. this can be used to place the module in a low power standby state. the ce bit should be set before the module is enabled for proper bringup. r/w 0
amd alchemy? au1000? processor data book - preliminary 159 uart interfaces 30360d 6.7.15 hardware considerations the uart signals are listed in table 6-34. fo r changing pin functionality please refer to the sys_pinfunc register in sec- tion 7.3 "general purpose i/o and pin functionality" on page 183. table 6-34. uart signals signal input/output definition uart0 u0txd o uart0 transmit. muxed with gpio[20]. u0 txd is the default signal coming out of hardware reset, runtime reset, and sleep. u0rxd i uart0 receive. uart1 u1txd o uart1 transmit. muxed with gpio[21]. u1 txd is the default signal coming out of hardware reset, runtime reset, and sleep. u1rxd i uart1 receive. uart2 u2txd o uart2 transmit. muxed with gpio[22]. u2 txd is the default signal coming out of hardware reset, runtime reset, and sleep. u2rxd i uart2 receive. uart3 u3txd o uart3 transmit. muxed with gpio[23]. u3 txd is the default signal coming out of hardware reset, runtime reset, and sleep. u3rxd i uart3 receive. u3cts i clear to send (optional). muxed with gpio[9]. gpio[9] is the default signal coming out of hardware reset, runtime reset, and sleep. system note : for systems that use the uart3 interface without the optional modem control signals ( sys_pinfunc [ur3]=0), the modem status interrupts must be disabled ( uart3_inten [mie]=0) to avoid false uart3 interrupts when using gpio[9], gpio[10], gpio[11], or gpio[12] as an input. u3dsr i data set ready (optional). muxed with gpio[10]. gpio[10] is the default signal coming out of hardware reset, runtime reset, and sleep. system note : for systems that use the uart3 interface without the optional modem control signals ( sys_pinfunc [ur3]=0), the modem status interrupts must be disabled ( uart3_inten [mie]=0) to avoid false uart3 interrupts when using gpio[9], gpio[10], gpio[11], or gpio[12] as an input. u3dcd i data carrier detect (optional). muxed with gpio[11]. gpio[11] is the default signal coming out of hardware reset, runtime reset, and sleep. system note : for systems that use the uart3 interface without the optional modem control signals ( sys_pinfunc [ur3]=0), the modem status interrupts must be disabled ( uart3_inten [mie]=0) to avoid false uart3 interrupts when using gpio[9], gpio[10], gpio[11], or gpio[12] as an input. u3ri i ring indication (optional). muxed with gpio[12]. gpio[12] is the default signal coming out of hardware reset, runtime reset, and sleep. system note : for systems that use the uart3 interface without the optional modem control signals ( sys_pinfunc [ur3]=0), the modem status interrupts must be disabled ( uart3_inten [mie]=0) to avoid false uart3 interrupts when using gpio[9], gpio[10], gpio[11], or gpio[12] as an input. u3rts o request to send (optional). muxed with gpio[13]. gpio[13] is the default signal coming out of hardware reset, runtime reset, and sleep. u3dtr o data terminal ready (optional). muxed with gpio[14]. gpio[14] is the default sig- nal coming out of hardware reset, runtime reset, and sleep.
160 amd alchemy? au1000? processor data book - preliminary ssi interfaces 30360d 6.8 ssi interfaces the au1000 processor contains two synchronous serial interfaces (ssis) designed to provide a simple connection to exter- nal serial devices. these serial channels support the ssi protocol and a subset of the spi protocol. each serial channel is independently programmable for various address and data lengths, clock rates, and behavior. each channel has a data in pin, data out pin, a clock pin, an d an enable pin. only master mode is supported. the au1000 processor drives the clock and enable pins when the interface is enabled. the data out pin will tri-state during a read, thus the data out pi n and data in pin can be tied together for a bidirectional data pin. 6.8.1 operation the ssi generates the clock output sclk. the clock is derived from the peripheral bus clock by a divider controlled by the ssi_clkdiv register. the clock only transitions when a transaction is in progress. the ssi contains a status register that reflects the current state. a busy bit is set when a transfer is initiated and cleared when ssi returns to idle. a done bit is set when the transfer is complete. the done bit may be used to signal an interrupt. 6.8.1.1 write transactions write transactions transfer data from the au1000 processor to a peripheral device attached to the ssi. the transaction con- sists of a data field and optional address and direction fields. the order of the address and direction fields is configurable. the address and direction fields may also be omitted from the tr ansaction. the data field is always the last field transmitted. the order of bit transmission within a field (msb first or lsb first) is also configurable. the sden output presents an envelope ar ound the transaction. figure 6-4 shows a typical write transaction. for this trans- action the address field is 3 bits long, data is 8 bits, and direction precedes address. figure 6-4. typical wr ite transaction timing 6.8.1.2 read transactions a read transaction is initiated by wr iting the address and direction to the ssi_adata register (the data field is ignored). the busy status bit will be set and will remain set until the done bit is set to indicate completion. once the transaction is com- plete the data may be read from the data field in ssi_adata . an extra clock cycle is inserted between the direction/ address transmission by the processor and the data field transmis- sion by the external device to avoid contention. the behavior of sclk may be changed during this extra cycle by program- ming the bm field in the ssi_config register. figure 6-5 shows a typical read transaction where the bus mode is set to hold sclk high during the bus turnaround. figure 6-5. typical read transaction timing sclk sden 0 a0 a1 a2 d0 d1 d2 d3 d5 d6 d7 sdout write transaction: alen = 2, dlen = 7, dp=1, dl = 0, ce = 0, ep = 0, ao = 0, do = 0 d4 sclk sden 1 a0 a1 a2 sdin read transaction: alen = 2, dlen = 7, dp=1, dl = 0, ce = 0, ep = 0, ao = 0, do = 0, bm = 00 d0 d1 d2 d3 d4 d5 d6 d7 sdout
amd alchemy? au1000? processor data book - preliminary 161 ssi interfaces 30360d 6.8.2 register description each ssi contains a register block used to configure the inte rface and to pass data. all registers must be written and read as 32 bit words. the locations of the register blocks for each ssi are shown in the table below. table 6-36 shows the offset and function of each register. 6.8.2.1 ssi interface status register the ssi_status register reflects the current status of the interface. table 6-35. ssi base addresses name physical base address kseg1 base address ssi0_base 0x0_1160_0000 0x_b160_0000 ssi1_base 0x0_1168_0000 0x_b168_0000 table 6-36. ssi registers offset register name description 0x0000 ssi_status ssi status register 0x0004 ssi_int ssi interrupt pending register 0x0008 ssi_inten ssi interrupt enable register 0x0020 ssi_config ssi configuration register 0x0024 ssi_adata ssi address/data register 0x0028 ssi_clkdiv ssi clock divider register 0x0100 ssi_enable ssi channel enable register ssi_status - ssi interface status offset = 0x0000 bit313029282726252423222120191817161514131211109876543210 bf of uf d b def.00000000000000000000000000000000 bits name description r/w default 31:5 ? reserved. should be cleared. r 0 4 bf buffer full. this bit indicates that the data buffer is currently full. it is set by either receiving a buffer from the seri al interface or a write by the proces- sor. it is cleared by either a transmit on the serial interface or a read by the processor. r0 3 of overflow. this bit is set when the se rial data register is written multiple times without completing an intervening transfer. this bit is sticky. once set high it must be written a ?1? to clear the bit. r/w 0 2 uf underflow. this bit is set when the se rial data register is read multiple times without an intervening serial transfer. this bit is sticky. once set high it must be written a ?1? to clear the bit. r/w 0 1 d done. this bit is set at the completion of an ssi transfer. this bit is sticky. once set high it must be written a ?1? to clear the bit. r/w 0 0 b busy. this bit is set if an ssi transfer is in progress r 0
162 amd alchemy? au1000? processor data book - preliminary ssi interfaces 30360d 6.8.2.2 interrupt pending register the ssi_int register shows which interrupt indications are currently active. 6.8.2.3 ssi interrupt enable register the ssi_inten register is writable by the processor and enables certain conditions on the ssi to generate an interrupt. the interrupt will be generated (and indicated in ssi_int ) when the corresponding bits are both set in ssi_inten and ssi_status . ssi_int - ssi interrupt pending register offset = 0x0004 bit313029282726252423222120191817161514131211109876543210 oi ui di def.00000000000000000000000000000000 bits name description r/w default 31:4 ? reserved, should be cleared. r 0 3 oi the oi bit indicates that the current interrupt is being generated by an overflow condition. this bit is sticky. once set high it must be written a ?1? to clear the bit. r0 2 ui the ui bit indicates that the current interrupt is being generated by an underflow condition. this bit is sticky. once set high it must be written a ?1? to clear the bit. r0 1 di the di bit indicates that the current interrupt is being generated by a done condition. this bit is sticky. once set high it must be written a ?1? to clear the bit. r0 0 ? reserved, should be cleared. r 0 ssi_inten - ssi interrupt enable register offset = 0x0008 bit313029282726252423222120191817161514131211109876543210 oie uie die def.00000000000000000000000000000000 bits name description r/w default 31:4 ? reserved. should be cleared. r 0 3 oie this bit enables interrupts on an overflow condition. r/w 0 2 uie this bit enables interrupts on an underflow condition. r/w 0 1 die this bit enables interrupts on a done condition. r/w 0 0 ? reserved. should be cleared. r 0
amd alchemy? au1000? processor data book - preliminary 163 ssi interfaces 30360d 6.8.2.4 ssi configuration register the ssi_config register contains fields which configure the operational parameters of the serial interface. ssi_config - ssi configuration register offset = 0x0020 bit313029282726252423222120191817161514131211109876543210 ao do alen dlen dd ad bm ce dp dl ep def.00000000000000000000000000000000 bits name description r/w default 31:25 ? these bits are reserved and should be written as 0. r 0 24 ao address field order. the ao bit select s the bit order of the address field. if ao is cleared the address field is se t lsb first. if ao is set the address field is sent msb first. r/w 0 23 do data field order. the do field sele cts the transmission order for the data field. if do is cleared the data field is sent lsb first. if do is set the data field is sent msb first. r/w 0 22:20 alen address field length. the alen field selects the length of the address field in the serial stream. the number of bits in the address field will be alen+1. r/w 0 19:16 dlen data field length. the dlen field selects the length of the data field in the serial stream. the number of bits in the data field will be dlen+1. values of dlen that result in a length greater than 12 are reserved and will result in undefined behavior. r/w 0 15:12 ? these bits are reserved and should be written as 0. r/w 0 11 dd direction bit disable. if the dd bit is se t the direction bit will not be sent. r/w 0 10 ad address field disable. if the ad bit is set the address field will not be sent. r/w 0 9:8 bm bus mode. determines the turnaround behavior for read cycles. 00 sclk held high during turnaround. 01 sclk held low during turnaround. 10 sclk cycles during turnaround. 11 reserved r/w 0 7 ce the ce bit determines which clock edge is active for sclk. if ce is cleared data and address will be clocked out on the negative edge and captured at the positive edge. if ce is set data and address will be clocked out on the positive edge and captured on the negative edge. r/w 0 6 dp direction polarity. determines whether a write is indicated by an active- high or active-low direction bit. 0 a write is indicated by an active-high direction bit. 1 a write is indicated by an active-low direction bit. r/w 0 5 dl direction bit location. if the dl bit is clear the direction bit is sent before the address bits in the serial stream. if dl is set the direction bit will follow the address field. r/w 0 4 ep enable polarity. selects the polarity of the enable signal on the interface. 0 enable is active high. 1 enable is active low. r/w 0 3:0 ? reserved. should be cleared. r/w 0
164 amd alchemy? au1000? processor data book - preliminary ssi interfaces 30360d 6.8.3 ssi address/data register the ssi_adata register contains the address, dat a, and direction fields. writing to ssi_adata will initiate a transfer. the type of transfer (read or write) is det ermined by the d (direction) bit. 6.8.3.1 ssi clock divider register the ssi_clkdiv register determines the baud rate of the se rial port. the baud rate is defined as follows: baudrate = cpu / (sd * 4 * ( clkdiv + 1)) cpu = cpu clock sd = system bus divider (see section 7.4 "power management" on page 188 for information on sd.) ssi_adata - ssi address/data register offset = 0x0024 bit313029282726252423222120191817161514131211109876543210 d addr data def.00000000000000000000000000000000 bits name description r/w default 31:25 ? reserved. should be cleared. r 0 24 d direction bit. 0 the transaction is a read, and the data field contains the value of the serial input at the end of the transaction. 1 the transaction is a write. r/w 0 23:16 addr address field. r/w 0 15:12 ? reserved. should be cleared. r 0 11:0 data data field. r/w 0 ssi_clkdiv - ssi clock divider offset = 0x0028 bit313029282726252423222120191817161514131211109876543210 clkdiv def.00000000000000000000000000000000 bits name description r/w default 31:16 ? reserved. should be cleared. r 0 15:0 clkdiv the clkdiv field determines the baud rate of the interface. r/w 0
amd alchemy? au1000? processor data book - preliminary 165 ssi interfaces 30360d 6.8.3.2 ssi enable register the ssi_enable register allows the serial interface to be disabled or placed in a low power mode . the correct routine for bringing the ssi block out of reset is as follows: 1) clear the cd bit to enable clocks. 2) set the e bit to enable the peripheral. ssi_enable - ssi enable register offset = 0x0100 bit313029282726252423222120191817161514131211109876543210 cd e def.00000000000000000000000000000010 bits name description r/w default 31:2 ? reserved. should be cleared. r 0 1cd clock disable. 0 enable the clock to the ssi block. 1 disable (disconnect) the clock to the ssi block. w1 0e enable. 0 hold the ssi block in reset. 1 enable the ssi block. w0
166 amd alchemy? au1000? processor data book - preliminary ssi interfaces 30360d 6.8.4 hardware considerations the ssi ports consist of the signals listed in table 6-37. for changing pin functionality please refer to the sys_pinfunc reg- ister in section 7.3 "general purpose i/o and pin functionality" on page 183. table 6-37. ssi signals signal input/output definition ssi0 s0clk o master only clock output. the speed and polarity of clock edge is programmable. muxed with gpio[17]. s0din i serial data input. this signal may be tied with s0dout to create a single bidirec- tional data signal. s0dout o serial data output. this signal is in tri-state during a read and thus may be tied to s0din to create a single bidirectional data signal. muxed with gpio[16]. s0den o enable signal which frames transa ction. the polarity is programmable. muxed with gpio[18]. ssi1 s1clk o master only clock output. the speed and polarity of clock edge is programmable. muxed with acdo which controls the pin ou t of hardware reset, runtime reset and sleep. s1din i serial data input. this signal may be tied with s1dout to create a single bidirec- tional data signal. muxed with acbclk which controls the pin out of hardware reset, runtime reset and sleep. s1dout o serial data output. this signal is in tri-state during a read and thus may be tied to s1din to create a single bidirectional data signal. muxed with acsync which controls the pin out of hardware reset, runtime reset and sleep. s1den o enable signal which frames transa ction. the polarity is programmable. muxed with acrst# which controls the pin out of hardware reset, runtime reset and sleep.
amd alchemy? au1000? processor data book - preliminary 167 7 system control 30360d 7.0 system control the au1000 processor contains a robust system control st rategy that includes the means to control the following: clocking (see section 7.1 "clocks" on page 168.) time of year and real time clock counters (see section 7.2 "time of year clock and real time clock" on page 178.) gpio control (see section 7.3 "general purpose i/o and pin functionality" on page 183.) power management (see section 7. 4 "power management" on page 188.) all registers in the system control block are loca ted off of the base address shown in table 7-1. the registers in the system control block are affected differently by events such as power-on hardware reset, sleep and runtime reset (see section 8.0 "power-up, reset and boot" on page 196 for a discussion on the different reset types). each register is documented with how it will be affected by the different system states . care should be taken by the system designer to observe what registers will and will not re vert to defaults when the different events occur. table 7-1. system control block base address name physical base address kseg1 base address sys_base 0x0_1190_0000 0x_b190_0000
168 amd alchemy? au1000? processor data book - preliminary clocks 30360d 7.1 clocks the au1000 processor supports two oscillator inputs: 12 mhz and 32.768 khz. this section documents the clock domains driven directly and indirectly by the 12 mhz input. the 32.768 khz clock input drives the two programmable counters intended for use as a real time clock (rtc) and time of year clock (toy). the programmable counters are documented in section 7.2 "time of year clock and real time clock" on p age 178. (see section 11.8 "crystal specifications" on page 253 for the specifications of both crystals.) the au1000 processor contains two plls driven by the 12 mhz oscillator and a clocking block from which the following are derived: cpu clock core cycle counter register clocked by the cpu clock system bus clock peripheral bus clock sdram bus clock programmable clocks needed by certain peripherals programmable clocks extclk[1:0] for external use (p rovided on pins shared with the gpio[3:2] signals) figure 7-1 shows the basic clocking topology and the relati onship between the cpu clock, the system bus clock and the peripheral clock. as shown, the system bus frequency is de rived by dividing the cpu clock by the value sd programmed in the sys_powerctrl register. (see section 7.4 "power management" on page 188 for the sys_powerctrl register defini- tion.) the peripheral bus clock and the sdram bus are fixed at the system bus frequency divided by 2. figure 7-1 also shows the peripheral blocks driven by clock sources derived from the programmable clock generator logic (as described in section 7.1.2, "clock generation"). figure 7-1. clocking topology 12.000 mhz cpu clock system bus clock peripheral bus clock /2 /sd* cpu_pll aux_pll clock generator irda usb device usb host i2sclk extclk0 extclk1 sdram bus clock /2 auxiliary clock *sd is a programmable field in the sys_powerctrl register as described in section 7.4.4 "power man- agement registers" on page 191. sd can be 2, 3, or 4.
amd alchemy? au1000? processor data book - preliminary 169 clocks 30360d 7.1.1 clock register descriptions the clock manager registers and their associated offsets are listed in table 7-2. 7.1.2 clock generation this section documents registers for the clock generation block which provides clocks to some peripheral devices and as well as two externally available clocks. the clock generation sub system is split into two sets of distinct blocks which allows up to six distinct frequencies to drive up to six clock sources. figure 7-2 shows a logical repr esentation of one of the six identical frequency generators and how the six frequency sources are mapped to one of the six identical internal clock sources. the names in the figure correspond to the bit names in the control registers. figure 7-3 shows a pictorial repre- sentation of the relationship between the frequen cy generator blocks to the clock source blocks. each peripheral has clock restrictions as follows. if these re strictions are not met, the peripheral will not operate correctly . the irda clock must be programmed to match value set in cs . cs is the phy layer clock speed field in the ir_config2 register. see section 6.4 "irda" on page 108 for more information. the usb device clock must be programmed to 48 mhz. the usb host clocks must be programmed to 48 mhz. the i2sclk must be set to match the effective bit rate which will be determined by the sampling frequency (system depen- dent) times the bit rate (2 * sz ). sz is the size field in the i2s_config register. the extclk[1:0] clocks can be prog rammed for system use. if the i 2 s peripheral is being used, typically one of these clocks will be programmed to provide the system oversampling clock for the codec (i.e. 128 fs, 256fs, or 512fs where fs is the system sampling frequency). note that the extclk[1:0] clocks have a maximum frequency rating of (f max / 16), where f max is the maximum frequency rating for the part. for example, for a 400 mhz part be sure the extclk[1:0] clocks are programmed to run at no more than 25 mhz. (see also section 11.7 "ext ernal clock specifications" on page 252.) note also that the extclk[1:0] clocks are multiplexed signals and require programming of the sys_pinfunc register (see section 7.3.1.1 "pin function " on page 183) as follows: extclk0 shares a pin with gpio[2]. if extclk0 is to be used, sys_pinfunc [ex0] must be set to allow the clock to drive this pin. in addition, sys_pinfunc [cs] must be cleared. extclk1 shares a pin with gpio[3]. if extclk1 is to be used, sys_pinfunc [ex1] must be set to allow the clock to drive this pin. table 7-2. clock generation registers offset from 0x0_1190_0000 (physical) 0x_b190_0000 (kseg1) register name description reset type 0x0020 sys_freqctrl0 controls (source, enable, and di vider) frequency generators 0, 1, and 2 hardware 0x0024 sys_freqctrl1 controls (source, enable, and di vider) frequency generators 3, 4, and 5 hardware 0x0028 sys_clksrc controls (s ource and divider) the derived clocks hardware 0x0060 sys_cpupll changes cpu pll frequency hardware 0x0064 sys_auxpll changes auxiliary pll frequency hardware & runtime
170 amd alchemy? au1000? processor data book - preliminary clocks 30360d figure 7-2. frequency generator and clock source block diagram auxiliary clock cpu clock freq n 1 fs n fe n divide = (frdiv n + 1) * 2 0 /2 /4 auxiliary clock freq0 freq1 freq2 freq3 freq4 freq5 peripheral 0 1 2 3 4 5 6 7 m xx 0 1 0 1 d xx c xx frequency generator block clock source block reserved xx denotes the abbreviated peripheral name clock out
amd alchemy? au1000? processor data book - preliminary 171 clocks 30360d figure 7-3. frequency generator and clock source mapping freq. gen. block 1 cpu aux freq1 freq. gen. block 2 cpu aux freq2 freq. gen. block 3 cpu aux freq3 freq. gen. block 4 cpu aux freq4 freq. gen. block 0 cpu aux freq0 freq. gen. block 5 cpu aux freq5 aux freq1 freq2 freq3 freq4 freq5 irda clock source irda clock aux freq1 freq2 freq3 freq4 freq5 usb device clock usb dev clock aux freq1 freq2 freq3 freq4 freq5 usb host clock usb host clock aux freq1 freq2 freq3 freq4 freq5 i2sclk clock i2sclk aux freq1 freq2 freq3 freq4 freq5 gpio[2] clock extclk0 aux freq1 freq2 freq3 freq4 freq5 gpio[3] clock extclk1 block source block source block source block source block source block freq0 freq0 freq0 freq0 freq0 freq0
172 amd alchemy? au1000? processor data book - preliminary clocks 30360d 7.1.2.1 frequency control 0 this register controls t he frequency generator block for output frequencies 0, 1, and 2. this register will reset to defaults only on a hardware reset. during a runtime reset and during sleep this register will retain its value. sys_freqctrl0 offset = 0x0020 bit313029282726252423222120191817161514131211109876543210 frdiv2[7:0] fe2 fs2 frdiv1[7:0] fe1 fs1 frdiv0[7:0] fe0 fs0 def.00000000000000000000000000000000 bits name description r/w default 31:30 ? reserved. should be cleared. r 0 29:22 frdiv2 divider for frequency generator 2. the frequency divider is (frdiv + 1) * 2, where frdiv is the value programmed in this field. r/w 0 21 fe2 frequency generator output enable 2. 0 disable output. 1 enable output . r/w 0 20 fs2 frequency generator 2 source. 0cpu core clock. 1 auxiliary clock. r/w 0 19:12 frdiv1 divider for frequency generator 1. the frequency divider is (frdiv + 1) * 2, where frdiv is the value programmed in this field. r/w 0 11 fe1 frequency generator 1 output enable. 0 disable output. 1 enable output . r/w 0 10 fs1 frequency generator 1 source. 0cpu core clock. 1 auxiliary clock. r/w 0 9:2 frdiv0 divider for frequency generator 0. the frequency divider is (frdiv + 1) * 2, where frdiv is the value programmed in this field. r/w 0 1 fe0 frequency generator 0 output enable. 0 disable output. 1 enable output . r/w 0 0 fs0 frequency generator 0 source. 0cpu core clock. 1 auxiliary clock. r/w 0
amd alchemy? au1000? processor data book - preliminary 173 clocks 30360d 7.1.2.2 frequency control 1 this register controls t he frequency generator block for output frequencies 3, 4, and 5. this register will reset to defaults only on a hardware reset. during a runtime reset and during sleep this register will retain its value. sys_freqctrl1 offset = 0x0024 bit313029282726252423222120191817161514131211109876543210 frdiv5[7:0] fe5 fs5 frdiv4[7:0] fe4 fs4 frdiv3[7:0] fe3 fs3 def.00000000000000000000000000000000 bits name description r/w default 31:30 ? reserved. should be cleared. r 0 29:22 frdiv5 divider for frequency generator 5. the frequency divider is (frdiv + 1) * 2, where frdiv is the value programmed in this field. r/w 0 21 fe5 frequency generator 5 output enable. 0 disable output. 1 enable output . r/w 0 20 fs5 frequency generator 5 source. 0cpu core clock. 1 auxiliary clock. r/w 0 19:12 frdiv4 divider for frequency generator 4. the frequency divider is (frdiv + 1) * 2, where frdiv is the value programmed in this field. r/w 0 11 fe4 frequency generator 4 output enable. 0 disable output. 1 enable output . r/w 0 10 fs4 frequency generator 4 source. 0cpu core clock. 1 auxiliary clock. r/w 0 9:2 frdiv3 divider for frequency generator 3. the frequency divider is (frdiv + 1) * 2, where frdiv is the value programmed in this field. r/w 0 1 fe3 frequency generator 3 output enable. 0 disable output. 1 enable output . r/w 0 0 fs3 frequency generator 3 source. 0cpu core clock. 1 auxiliary clock. r/w 0
174 amd alchemy? au1000? processor data book - preliminary clocks 30360d 7.1.2.3 clock source control this register controls the clock source for all output clocks. this register will reset to defaults only on a hardware reset. d ur- ing a runtime reset and during sleep this register will retain its value. sys_clksrc offset = 0x0028 bit313029282726252423222120191817161514131211109876543210 me1[2:0] de1 cg3 me0[2:0] de0 ce0 mi2[2:0] di2 ci2 muh[2:0] duh cuh mud[2:0] dud cud mir[2:0] dir cir def.00000000000000000000000000000000 bits name description r/w default 31:30 ? reserved. should be cleared. r 0 29:27 me1 extclk1 clock mux input select. see table 7-3 on page 175. r/w 000 26 de1 extclk1 clock divider . 0 divide by 4. 1 divide by 2. r/w 0 25 ce1 extclk1 clock select. 0 clock is taken directly from mux. (the divider select bit de1 has no effect.) 1 clock is taken from 2/4 divider. r/w 0 24:22 me0 extclk0 clock mux input select. see table 7-3 on page 175. r/w 000 21 de0 extclk0 clock divider select. 0 divide by 4 1 divide by 2 r/w 0 20 ce0 extclk0 clock select. 0 clock is taken directly from mux. (the divider select bit de0 has no effect.) 1 clock is taken from 2/4 divider. r/w 0 19:17 mi2 i 2 s clock mux input select. see table 7-3 on page 175. r/w 000 16 di2 i 2 s clock divider select. 0 divide by 4. 1 divide by 2. r/w 0 15 ci2 i 2 s clock select. 0 clock is taken directly from mux. (the divider select bit di2 has no effect.) 1 clock is taken from 2/4 divider r/w 0 14:12 muh usb host clock mux input select. see table 7-3 on page 175. r/w 000 11 duh usb host clock divider select. 0 divide by 4. 1 divide by 2. r/w 0 10 cuh usb host clock select. 0 clock is taken directly from mux. (the divider select bit duh has no effect.) 1 clock is taken from 2/4 divider. r/w 0 9:7 mud usb device clock mux input select. see table 7-3 on page 175. r/w 000 6 dud usb device clock divider select. 0 divide by 4 1 divide by 2 r/w 0 5 cud usb device clock select. 0 clock is taken directly from mux. (the divider select bit dud has no effect.) 1 clock is taken from 2/4 divider. r/w 0 4:2 mir irda clock mux input select. see table 7-3 on page 175. r/w 000
amd alchemy? au1000? processor data book - preliminary 175 clocks 30360d the specific values written to the 3-bit clock-mux- input-select fields are shown in table 7-3. the freq n selections come from the output of the corresponding frequen cy generators, as shown in figure 7-2. 7.1.3 pll control there are two registers for controlling the two plls integrat ed into the au1000 processor. each pll is independently pro- grammable. note that when programming the pll control re gisters, the system designer must not violate the rated fre- quency limits of the au1000 processor. configuring the plls outside this frequency range causes undefined behavior. for higher frequencies the au1000 processor core requires a higher core voltage (v ddi ). care should be taken that the sys- tem is providing the correct voltage for the operating fr equency before changing the cpu clock. see section 11.3 "dc parameters" on page 236, for full information about the voltage/frequency requirem ents of the au1000 processor. the core cycle counter register located at cp0 regist er 9 can be used to count core cycles. please see section 2.7 "coprocessor 0" on page 28, for more information. the two plls in the au1000 processor drive the cpu clock and the auxiliary clock. the default pll multiplier value is 16 for the cpu clock and 0 for the auxpll which has the foll owing implications assuming a 12 mhz crystal on xti12 and xto12: cpu clock = 192 mhz auxiliary clock = disabled system bus clock = 96 mhz (sd - system bus divider - defaults to 2) peripheral bus = 48 mhz sdram bus = 48 mhz. when modifying the cpu clock frequency approximately 20 s elapse while the cpu and bus clocks shut off and the cpu pll locks to the new frequency. during this period instructions are not executed and interrupts are not serviced. interrupts are serviced once execution begins again at the new frequency. 1 dir irda clock divider select. 0 divide by 4. 1 divide by 2. r/w 0 0 cir irda clock select. 0 clock is taken directly from mux. (the divider select bit dir has no effect.) 1 clock is taken from 2/4 divider. r/w 0 table 7-3. clock mux input select values value meaning 000 no clocking 001 auxiliary clock 010 freq0 011 freq1 100 freq2 101 freq3 110 freq4 111 freq5 bits name description r/w default
176 amd alchemy? au1000? processor data book - preliminary clocks 30360d 7.1.3.1 cpu pll control the cpu pll control register ( sys_cpupll ) resets to its default value only for a hardware reset. that is, after sleep, and during a runtime reset the cpu pll retains its frequency. note that when programming the cpu pll control register the system designer mu st not violate the rated frequency limits of the au1000 processor. configuring the pll outsi de this frequency range causes undefined behavior. this register is read/write, but the value read is valid only after initialization. after coming out of reset, hardware reset o r sleep, this register must first be written for the value read back to be valid. for this reason it is suggested that this regis ter be initialized at boot time regardless if the value is changed from default. after writing to the sys_cpupll register, the system automatically halts for 20 s to allow for the pll to relock and clocks to become stable. sys_cpupll offset = 0x0060 bit313029282726252423222120191817161514131211109876543210 pll[5:0] def.00000000000000000000000000010000 bits name description r/w default 31:6 ? reserved. should be cleared. r/w 0 5:0 pll cpu pll multiplier. determines the integer multiplier used to multiply the cpu pll to generate the cpu clock. for example, with the default of 16 and a 12 mhz osc frequency, the cpu clock frequency is 192 mhz. note that pll multiplier values t hat place the clock frequency outside of rated limits are invalid. 0?15: reserved and undefined 16?( n -1): valid pll multiplier n ?63: reserved and undefined where n is the smallest pll multiplier that would cause the cpu clock fre- quency to exceed the rated frequency limits of the part. r/w 0x10
amd alchemy? au1000? processor data book - preliminary 177 clocks 30360d 7.1.3.2 auxiliary pll control the auxiliary pll control register ( sys_auxpll ) resets to its default value on hardware reset, after sleep, and during a runt- ime reset. this register is read/write, bu t the value read is valid only after initialization. for this reason it is recommende d that system software initialize this regist er at hardware reset, runtime reset and sleep, even if programming its default value. note that when programming the auxiliary pll control regi ster the system designer must not violate the rated frequency limits of the au1000 processor. configuring the pll outsi de this frequency range causes undefined behavior. unlike the sys_cpupll register, writing sys_auxpll does not cause the system to halt. as a consequence, clocks taken from the aux pll may be unstable for up to 20 s. to ensure stable clocks during aux pll lock time, the sys_cpupll reg- ister can be written with its current value to force the system to halt for 20 s. 7.1.4 hardware considerations note also that the extclk[1:0] clocks are multiplexed signals and require programming of the sys_pinfunc register (see section 7.3.1.1 "pin function " on page 183) as follows: when using the external clocks from the clock generation block, the sys_pinfunc register must be programmed such that gpio[2] and/or gpio[3] are configured to be driven by extclk0 and/or extclk1. section 11.8 "crystal specifications" on page 253, define the crystal specifications. 7.1.5 programming considerations when changing the cpu pll value through the sys_cpupll register, the system automatica lly halts for 20 s to allow clocks to stabilize. during this time no interrupts are serviced, potentially affecting real-time system s. however, modifying the sys_auxpll register does not cause the system to halt, a nd therefore clocks taken from the aux pll may be unstable for up to 20 s. to ensure stable clocks while the aux pll locks, the sys_cpupll register can be written with its current value to force the system to halt for 20 s. sys_auxpll offset = 0x0064 bit313029282726252423222120191817161514131211109876543210 pll[5:0] def.00000000000000000000000000000000 bits name description r/w default 31:6 ? reserved. should be cleared. r/w 0 5:0 pll auxiliary pll multiplier. determines the integer multiplier used to multiply the auxiliary pll to generate the auxiliary clock. for example, with a value of 12 and a 12 mhz osc frequency, the auxil- iary clock frequency will be 144 mhz. note that pll multiplier values t hat place the clock frequency outside of rated limits are invalid. 0: disable the auxiliary pll. 1?7: reserved and undefined 8?( n -1): valid pll multiplier n ?63: reserved and undefined where n is the smallest pll multiplier t hat would cause the auxiliary clock frequency to exceed the rated frequency limits of the part. r/w 0x00
178 amd alchemy? au1000? processor data book - preliminary time of year clock and real time clock 30360d 7.2 time of year clock and real time clock the au1000 processor contains two programmable counters designed for use as a time of year clock (toy) and real time clock (rtc). because the toy continues counting through slee p, a toy counter match can be used as a wake-up source. the rtc, however, will power-down in sleep mode. note that both the toy and rtc counters are driven by the 32.768-khz clock input. the clock input source can be a crystal or external clock. (see section 11.8 "crystal specifications" on page 253 for crystal details.) each programmable counter employs a register to initialize th e counter or load a new value, a trim divider to adjust the incoming 32.768-khz clock, and three match registers which have associated interrupts that trigger on a match. each counter is also able to generate an interrupt on every tick. all interrupts are maintained through the interrupt controller. bo th programmable counters share a status register. figure 7-4 shows the functional block diagram of both the to y and the rtc. the registers used to implement the block, including the counter control register ( sys_cntrctrl ), are described in the following section. figure 7-4. toy and rtc block diagram 1 divide = trim + 1 0 toy counter match0 match1 match2 comparators interrupt interrupt interrupt interrupt 32.768 khz sys_cntrctrl [eo] sys_cntrctrl [btt] 1 0 gpio[8] sys_cntrctrl [bp] divide = trim + 1 rtc counter match0 match1 match2 comparators interrupt interrupt interrupt interrupt sys_cntrctrl [brt] 1 0
amd alchemy? au1000? processor data book - preliminary 179 time of year clock and real time clock 30360d 7.2.1 time of year clock and real time clock registers each counter operates identically with the only difference being that the toy continues counting through sleep and the rtc does not. the programmable counter control registers and their associated offsets are listed in table 7- 4. when functionality is iden- tical for registers in the different programmable counters, only one general register descrip tion is presented with offsets pointing to the specific registers. 7.2.1.1 trim register the toy trim write status bit ( sys_cntrctrl [tts]) must be clear before writing sys_toytrim . it is set upon writing this regis- ter and is cleared by hardware when the write takes effect. the rtc trim write status bit ( sys_cntrctrl [rts]) must be clear before writing sys_rtctrim . it is set upon writing this regis- ter and is cleared by hardware when the write takes effect. this register is unpredictable at powe r-on. during a runtime reset and during sl eep this register retains its value. table 7-4. programmable counter registers offset from 0x0_1190_0000 (physical) 0x_b190_0000 (kseg1) register name description reset type 0x0000 sys_toytrim trim value for 32.768- khz clock source for toy hardware 0x0004 sys_toywrite toy counter value is wr itten through this register. hardware 0x0008 sys_toymatch0 toy match 0 valu e for interrupt generation hardware 0x000c sys_toymatch1 toy match 1 valu e for interrupt generation hardware 0x0010 sys_toymatch2 toy match 2 valu e for interrupt generation hardware 0x0014 sys_cntrctrl control register for toy and rtc hardware 0x0040 sys_toyread toy counter value is read from this register hardware 0x0044 sys_rtctrim trim value for 32.768- khz clock source for rtc hardware 0x0048 sys_rtcwrite rtc counter value is wr itten through this register. hardware 0x004c sys_rtcmatch0 rtc match 0 value for interrupt generation hardware 0x0050 sys_rtcmatch1 rtc match 1 value for interrupt generation hardware 0x0054 sys_rtcmatch2 rtc match 2 value for interrupt generation hardware 0x0058 sys_rtcread rtc counte r value is read from this register. hardware sys_toytrim - toy trim offset = 0x0000 sys_rtctrim - rtc trim offset = 0x0044 bit313029282726252423222120191817161514131211109876543210 trim[15:0] def.0000000000000000 xxxxxxxxxxxxxxxx bits name description r/w default 31:16 ? reserved. should be cleared. r 0 15:0 trim divide value for 32.768khz input. divide = trim + 1 r/w unpred
180 amd alchemy? au1000? processor data book - preliminary time of year clock and real time clock 30360d 7.2.1.2 counter write the toy value write status bit ( sys_cntrctrl [ts]) must be clear before writing sys_toywrite . it is set upon writing this reg- ister and is cleared by hardware when the write takes effect. the rtc value write status bit ( sys_cntrctrl [rs]) must be clea r before writing sys_rtcwrite . it is set upon writing this reg- ister and is cleared by hardware when the write takes effect. this register is unpredictable at powe r-on. during a runtime reset and during sl eep this register retains its value. 7.2.1.3 match registers the corresponding write status bit ( sys_cntrctrl [tm n ] or sys_cntrctrl [rm n ]) must be clear before writing the below regis- ters. it is set upon writing the register and is cleared by hardware when the write takes effect. each match register is capable of causing an interrupt as shown in section 5.0 "interrupt controller" on page 81. the sys_toymatch2 can be used to wake up from sleep; see sect ion 7.4.4.2 "wakeup source mask register" on page 192. see also section 7.2.2. these registers are unpredictable at powe r-on. during a runtime reset and during sleep these registers retain their value. sys_toywrite - toy counter value write offset = 0x0004 sys_rtcwrite - rtc counter value write offset = 0x0048 bit313029282726252423222120191817161514131211109876543210 count[31:0] def.xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx bits name description r/w default 31:0 count counter write. the respective c ounter will be updated with the value writ- ten to this register at the next trimmed clock. w unpred sys_toymatch0 - toy match 0 offset = 0x0008 sys_toymatch1 - toy match 1 offset = 0x000c sys_toymatch2 - toy match 2 offset = 0x0010 sys_rtcmatch0 - rtc match 0 offset = 0x004c sys_rtcmatch1 - rtc match 1 offset = 0x0050 sys_rtcmatch2 - rtc match 2 offset = 0x0054 bit313029282726252423222120191817161514131211109876543210 match[31:0] def.xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx bits name description r/w default 31:0 match a match with the counter and the value in this register causes an interrupt. r/w unpred
amd alchemy? au1000? processor data book - preliminary 181 time of year clock and real time clock 30360d 7.2.1.4 toy and rtc counter control the toy and rtc counter control register ( sys_cntrctrl ) contains control bits and status bits to co nfigure and control both programmable counters. write status bits: these bits indicate the status of the latest update to the respective register/field. when the corresponding register/field is written, this bit is set indicating that there is a write pending. when this bi t is cleared the write has tak en place. software should poll the correct bit and insure that it is 0 before updating the respective register/field. this register resets to default values only on a hardware reset. during a runtime reset and during sleep this register retains its value. sys_cntrctrl offset = 0x0014 bit313029282726252423222120191817161514131211109876543210 rtsrm2rm1rm0 rs bp brt btt eo ccs 32s tts tm2 tm1 tm0 ts def.00000000000000000000000000x00000 bits name description r/w default 31:21 ? reserved. should be cleared. r 0 20 rts sys_rtctrim write status. sys_rtcmatch2 write status. sys_rtcmatch1 write status. sys_rtcmatch0 write status. sys_rtcwrite write status. 0 no write is pending. it is safe to write to the register. 1 a write is pending. do not write to the register. r0 19 rm2 r0 18 rm1 r0 17 rm0 r0 16 rs rr 15 ? reserved. should be cleared. r 0 14 bp bypass the 32.768-khz osc. 0 select oscillator input (xti32, xto32) 1 gpio[8] drives the counters. this is a test mode where gpio[8] can drive the counters from an external source or through software using the gpio controller. r/w 0 13 ? reserved. should be cleared. r/w 0 12 brt bypass rtc trim. 0 normal operation 1 the rtc is driven directly by the 32.768 khz clock, bypassing the trim. r/w 0 11 ? reserved. should be cleared. r/w 0 10 btt bypass toy trim. 0 normal operation 1 the toy is driven directly by the 32.768 khz clock, bypassing the trim. r/w 0 9 ? reserved. should be cleared. r 0 8 eo enable 32.768-khz oscillator. enables the clock for the rtc/toy block. 0 disable the clock. 1 enable the clock. regardless of the clock source (cryst al or overdriven clock through xti32/ xto32, or bypass through gpio[8]), the eo bit must be set to enable the rtc/toy counters. after enabling the clock by setting eo, poll the oscilla- tor status bit (32s) until it returns a ?1?. once 32s is set, wait an additional one second to allow for frequency st abilization within the block before accessing other rtc/toy r egisters (not including sys_cntrctrl ). note: if the oscillator is being ov erdriven or bypassed through gpio[8], be sure to set eo only after a stable clock is being driven into the part. r/w 0 7 ccs sys_cntrcntrl write status. r 0 6 ? reserved. should be cleared. r 0
182 amd alchemy? au1000? processor data book - preliminary time of year clock and real time clock 30360d 7.2.2 programming considerations to change the values of the counter and match registers, so ftware must poll the state of the corresponding status bit in sys_cntrctrl . when the corresponding write status bit ( sys_cntrctrl [tts,tm n ,ts] or sys_cntrctrl [rts,rm n ,rs]) is 0 it is okay to write a new value. once the new value is written to th e register the status bit will change to a 1. when the write sta- tus bit is 1 the new value is being updated in supporting hard ware. when the write status changes to a 0 then the new value is active in the device. 5 32s 32.768 khz oscillator status. detects two consecutive 32 khz cycles from the clock source for the rtc/toy block. 0 clock is not running. 1 clock is running. note: be sure to wait 1 second after 32s is set to allow for frequency stabi- lization within the block before accessing rtc/toy registers. r unpred 4 tts sys_toytrim write status. sys_toymatch2 write status. sys_toymatch1 write status. sys_toymatch0 write status. sys_toywrite write status. 0 no write is pending. it is safe to write to the register. 1 a write is pending. do not write to the register. r0 3tm2 r0 2tm1 r0 1tm0 r0 0ts r0 bits name description r/w default
amd alchemy? au1000? processor data book - preliminary 183 general purpose i/o and pin functionality 30360d 7.3 general purpose i/ o and pin functionality this section covers the programming model for the genera l purpose i/o (gpio) signals. the au1000 processor supports 32 gpios. this section also documents how to ch ange the functionality of multiplexed pins . these pins can function at the system level as a gpio signal, or they can be assigned a signal function dedicated to an integrated peripheral device. each gpio can be configured as either an in put or an output. the gpio ports also can be connected to the internal inter- rupt controllers to generate an interrupt from input signals. s ee section 5.0 "interrupt controller" on page 81 for information on interrupts. 7.3.1 pin functionality to maximize the functionality of the au1000 processor, many of the pins have multiple uses. note that if a pin is pro- grammed for a certain use, any other functionality associated wi th that pin can not be utilized at the same time. in other words, a pin can not be used as a gpio at the same time it is assigned to a peripheral device. (for reference, figure 10-1 "au1000? processor external signals" on page 217 shows a block diagram of all external sig- nals. signals that are multiplexed on one pin will show the shared function in parentheses.) 7.3.1.1 pin function this register resets to its default state at hardware reset, runtime reset and sleep. sys_pinfunc offset = 0x002c bit313029282726252423222120191817161514131211109876543210 cs usb u3 u2 u1 src ex1 ex0 rf ur3 i2d i2s ni2 u0 rd a97 s0 def.00000000000000000000000000000000 bits name description r/w default 31:17 ? reserved. should be cleared. r 0 16 cs clock select. applies only when ex0 = 1. 0 extclk0 will drive pin. 1 32-khz osc clock will drive pin. r/w 0 15 usb usb functionality. 0 usbdp and usbdm will drive pins (pins are connected to usb device module). 1 usbh0p and usbh0m will drive pins (pins are connected to usb host port 0). r/w 0 14 u3 uart3/gpio[23]. 0 u3txd drives pin. 1 pin is configured for gpio[23]. r/w 0 13 u2 uart2/gpio[22]. 0 u2txd drives pin. 1 pin is configured for gpio[22]. r/w 0 12 u1 uart1/gpio[21]. 0 u1txd drives pin. 1 pin is configured for gpio[21]. r/w 0 11 src gpio[6]/smromcke. 0 pin is configured for gpio[6]. 1 smromcke drives pin. r/w 0 10 ex1 gpio[3]/extclk1. 0 pin is configured for gpio[3]. 1 extclk1 will drive pin. r/w 0 9 ex0 gpio[2] / (extclk0 or 32khz osc). 0 pin is configured for gpio[2]. 1 pin is configured for extclk0 or 32 khz osc. cs (bit 16) selects whether extclk0 or the 32 khz osc drives the pin. r/w 0
184 amd alchemy? au1000? processor data book - preliminary general purpose i/o and pin functionality 30360d 8 irf gpio[15]/irfirsel. 0 pin is configured for gpio[15]. 1 irfirsel will drive pin. r/w 0 7 ur3 gpio[14:9]/uart3. 0 pins are configured as gpio[14:9]. 1 pins are configured for optional uart3 flow control. u3dtr, u3rts, u3ri, u3dcd, u3dsr, and u3cts will drive pins. system note : for systems that use the uart3 interface but do not use the optional modem control signals (ur3=0), the modem status interrupts must be disabled ( uart3_inten [mie]=0) to avoid false uart3 interrupts when using gpio[9], gpio[10], gpio[11], or gpio[12] as an input. r/w 0 6 i2d gpio[8]/i2sdi. 0 pin is configured for gpio[8]. 1 pin is configured as i2sdi. system note : for systems that use the i 2 s interface for unidirectional operation (i2sdi not used), the gpio[8] function is available but with the following restrictions: 1) when i2sdio is configured as an input , gpio[8] can be used only as an output. 2) when i2sdio is configured as an output , the i 2 s receive function must be disabled if gpio[8] is to be used as an input. r/w 0 5i2s i 2 s/gpio[31:29]. 0 pins are configured for i 2 s mode. i2sword, i2sclk, i2sdio will drive pins. 1 pins are configured as gpio[31:29]. r/w 0 4 ni2 mac1/gpio[28:24]. 0 pins are configured as ethernet port 1. n1txd[3:0], and n1txen will drive port. 1 pins are configured as gpio[28:24]. r/w 0 3 u0 uart0/gpio[20]. 0 pin is configured for u0txd (necessary for uart0 operation). 1 pin is configured as gpio[20]. r/w 0 2 ird irda/gpio[19]. 0 pin is configured for irtxd (necessary for irda operation). 1 pin is configured as gpio[19]. r/w 0 1 a97 ac97/ssi_1. 0 pins are configured for ac97 mode. acsync, acbclk, acdo, acrst# will drive pins. 1 pins are configured for ssi_1 mode. s1dout, s1din, s1clk and s1den will drive pins. r/w 0 0 s0 ssi_0/gpio[16:18]. 0 pins are configured for ssi_0 mode. s0clk, s0dout and s0den will drive pins. 1 pins are configured as gpio[16:18]. r/w 0 bits name description r/w default
amd alchemy? au1000? processor data book - preliminary 185 general purpose i/o and pin functionality 30360d 7.3.2 gpio control registers the gpios on the au1000 processor have been designed to simp lify the gpio control process by removing the need for a semaphore to control access to the register s. this is because there is no need to read, modify, write, as there are separate registers for setting and clearing a bit. in this way a functi on can freely manipulate its asso ciated gpios without interfering with other functions. figure 7-5 shows the logical implementatio n of each gpio. the names represent bit n of the corresponding register which affect gpio[n]. figure 7-5. gpio logic diagram the following table shows the gpio control registers and the asso ciated offsets from sys_base . certain registers share offsets and have different functionality depending on whether t he access is a read or a write. the register descriptions detail the functionality of each register. bit n of a particular register should be associated with gpio[n] for all registers except sys_pininputen . table 7-5. gpio control registers offset from 0x0_1190 0000 (physical) 0x_b190_0000 (kseg1) register name register description default 0x0100 sys_trioutrd the tri-state/ou tput state register shows the current state of the gpio. 0 gpio[n] is in tri-state. to tri-state gpio[n] is accomplished by setting the corre- sponding bit in the sys_trioutclr register. 1 output is enabled. enabling gpio[n] as an output is accomplished by programming gpio[n] as a 0 or 1 using the sys_outputclr [n] or sys_outputset [n] regis- ters. if the pin is not an output it should be in tri- state. 0x00000000 (all gpios are tri-state) 0x0100 sys_trioutclr sys_outputrd [n] sys_outputset [n] sys_outputclr [n] r s s-r r s s-r sys_trioutrd [n] sys_pinstaterd [n] sys_trioutclr [n] pin
186 amd alchemy? au1000? processor data book - preliminary general purpose i/o and pin functionality 30360d 7.3.2.1 gpio cont rol registers each gpio control register is 32 bits wide with bit n in each register affecting gpio[n]. these registers will reset to defaults only on a hardware rese t. during a runtime reset and during sleep this register will retain its value. see table 7-5 for the default values at hardware reset. certain registers in the list have the same offset but offer different functionality depending on whether a read or a write is being performed. registers ending in *rd, *set and *clr have the following functionality: *rd registers are read only registers will read back the current value of the register. *set registers are write only registers and will set to 1 all bi ts that are written 1. writing a value of 0 will have no impact on the corresponding bit. *clr registers are write only registers and will clear to zero all bits that are written 1. writing a value of 0 will have no impact on the corresponding bit. 0x0108 sys_outputrd controls the stat e of the gpio[n] as an output. 0 to output a low level, set sys_outputclr [n]. 1 to output a high level, set sys_outputset [n]. programming a bit value in the output register brings the pin out of tri-state mode and enables the output. unpred 0x0108 sys_outputset 0x010c sys_outputclr 0x0110 sys_pinstaterd allows the pin state to be read when an input. this register will also give the output state. unpred 0x0110 sys_pininputen any write to this register allows gpio[31:0] to be used as inputs. this register must be written before any gpio can be used as an input, an interrupt source, or for use as a wake up source. unpred *rd *set *clr bit313029282726252423222120191817161514131211109876543210 func[31:0] bits name description r/w default 31:0 func[n] the function of each register is given in the previous table. func[n] controls the functionality of gpio[n]. *_read - read only *_set - write only *_clear - write only see the following text. 0 table 7-5. gpio control registers (continued) offset from 0x0_1190 0000 (physical) 0x_b190_0000 (kseg1) register name register description default
amd alchemy? au1000? processor data book - preliminary 187 general purpose i/o and pin functionality 30360d 7.3.2.2 gpio input enable the sys_pininputen is a 32-bit, write-only register. when this register is written, the input fu nctionality of all gpios is enabled. this register enables gpios for use as an input but do es not explicitly configure a ll gpios as inputs. the value of the gpio control registers and the pin function register will define the state of each gpio. gpios cannot be used as inputs until this re gister is written. this write is required only once per hardwa re reset (i.e. sleep and a runtime reset will not require another write to this register). 7.3.3 hardware considerations the system pin func tion register ( sys_pinfunc ) controls the functionality of many gpio/peripheral pins. if a pin is pro- grammed for a certain functionality, all other fu nctionality associated with that pin is disabled. for example, if sys_pinfunc [u3] is cleared configuring the pin as u3txd, gpio[23] can not be us ed as a gpio nor can the gpio be configured as an interrupt. conversely if sys_pinfunc [u3] is set configuring the pin as gpio[23], u3txd (and thus the uart3 interface) is not usable. gpio[23] can be used as a gpio and to generate interrupts. 7.3.4 using gpio for external dma requests see section 4.2 "using gpio as external dma re quests (dma_reqn)" on page 78 for information. sys_pininputen offset = 0x0110 bit313029282726252423222120191817161514131211109876543210 en def.xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx bits name description r/w default 31:1 ? reserved. should be cleared. w n/a 0 en a write to this bit (0 or 1) enab les all gpios to be used as inputs. w n/a
188 amd alchemy? au1000? processor data book - preliminary power management 30360d 7.4 power management the au1000 processor contains a robust power management scheme allowing multiple levels of power conservation to enable the system designer options depending on whether power conservation or system responsiveness is more critical. in the au1000 processor, power management can be broken into three different areas: cpu peripherals device the lowest power state consists of putting the entire device into a sleep stat e. the cpu also supports two idle states that differ as to whether bus snooping is supported. in additi on each peripheral can have its clocks disabled when not in use thus significantly reducing the power draw by those blocks not in use. the flow chart in figure 7-6 shows the different stages of power management for the cpu (idle0,1) and the device (sleep) and how each state is entered an d left. note that any interrupt can be us ed to bring the cpu out of either idle state while only a gpio[7:0] or sys_toymatch2 interrupt can be enabled (in sys_wakemsk ) to bring the device out of sleep. figure 7-6. sleep and idle flow diagram prepare to sleep - flush cache - sdram sleep - turn off peripherals - enable sleep power - set sleep bit execute wait0 sleep idle0 idle1 execute wait1 wakeup enabled interrupt wakeup enabled interrupt ye s ye s ye s normal operation (no snoop) (snoop) reboot toy match or gpio[7:0] interrupt
amd alchemy? au1000? processor data book - preliminary 189 power management 30360d 7.4.1 cpu power management - idle the cpu can be put into 2 different low-power idle mode s (idle0 and idle1) by using the wait instruction: in the idle0 state the cpu snoops the bus and cache coherency is maintained. in the idle1 state the cpu does not snoop the bus and cache coherency is lost. the wait instruction and at least 4 instru ctions following it must be in the cache for the wait to occur. see section 2.6.3 "wait instruction" on page 27 for more information. at all times the mmu, data cache, execution and multiply-and -accumulate blocks are placed in a low power state if they are not being used. 7.4.1.1 returning from idle the processor wakes from the idle state (idle0 or idle1) upo n receiving an interrupt. the time required for the processor core to return to normal execution is as follows: five to ten cpu clocks are needed to restart clocks to the cpu. it takes an additional ten cpu clocks for the core to recognize the interrupt and begin fetching the interrupt service routine. therefore, a maximum of 20 cpu clocks are required to resume normal instruction pipeline execution. if the interrupt ser- vice routine is in the instruction cache, the instruction re turns immediately; otherwise, t here is an additional delay while fetching the instruction from memory. 7.4.2 peripheral power management peripheral power management is handled through clock managem ent and disabling of unused peripherals. table 7-6 lists the peripherals and their related power management registers. the actual register descriptions should be referred to for programming details. note that when separate reset/peripheral enable and clock-en able bits are provided, the reset must be applied first, and then the clocks should be disabled. this will simplify programmin g, as the suggested bring up sequence is typically to first enable clocks and then subsequently to bring the peripheral out of reset. table 7-6. peripheral power management peripheral power management register power management strategy usb host usbh_enable when the usb host is not in use the e bit can be cleared to disable the host. the ce bit should also be cleared to disable clocks to the block. usb device usbd_enable when the usb device is not in use the e bit can be cleared to disable the host. the ce bit should also be cleared to disable clocks to the block. ethernet mac n macen_mac n when either block is not being used, the respective e[2:0] bits should be cleared to disable the mac, and the ce bit should be cleared to gate clocks to the mac. uart n uart n _enable when a uart is not being used, the e bit should be cleared to hold the part in reset and the ce bit should be cleared to disable clocks to the block. ssi n ssi n _enable when an ssi is not being used, clear the e bit to hold the block in reset, and set the cd bit to disable clocks to the block. irda ir_enable the hc bit can be used to run the irda at half the system bus. the ce bit should be disabled when not using the irda to disable clocks to this peripheral. general-purpose i/o (gpio) controller sys_trioutclr although there is not a specific low-power configuration for the gpios, tristating the unused gpios minimizes their power usage.
190 amd alchemy? au1000? processor data book - preliminary power management 30360d 7.4.3 device power management - sleep the sleep state of the au1000 processor puts the entire device into a low-power state. sleep is the lowest power state of the part and requ ires a complete system initialization on wakeup. ther e are multiple steps to ta ke when going into sleep and waking up to insure data inte grity. during this state all registers values outs ide the system control block are lost and cache coherency is not maintained. the programmable counter 0 (intended for toy) continues clocking and remains functional during sleep. however, the programmable counter 1, as well as other clocks throughout the au1000 , are disabled during sleep. when coming out of sleep there is a programmable delay defined by sys_powerctrl [vput]. this is the time that the sys- tem designer has to ensure v ddi is stable from the rising edge of pwr_en. to enter sleep the following st eps should be taken. this co de should be run from flash, or conversely the system program- mer should guarantee that this code will run from cache because after sdram is put into auto-refresh mode, memory accesses will no longer work. 1) enable sleep power by writing to the sys_slppwr register. 2) turn off all peripherals. (explicitly turning off all peripherals in use ensures a graceful transition to sleep mode.) 3) push dirty data out of the cache. (during sleep cached data is lost.) 4) if sdram contents are to be kept through sleep, sdra m should be put into auto-re fresh mode. see section 3.1 "sdram memory controller" on page 44 for more information. if sdram is not needed to be maintained through sleep, disable the sdram. 5) if using one of gpio[7:0] as a wakeup source, sys_pininputen must be written to enable the gpio as an input if this has not already been done at system startup. 6) the sys_wakemsk register should be set with the appropriate value according to what signal(s) should wake the pro- cessor. 7) the sys_wakesrc register should be written to explic itly clear any pending wake interrupts. 8) enable sleep by writing to the sys_sleep register. this step puts the system to sleep. 9) as the system enters sl eep mode, the pwr_en signal is nega ted. this can be used to disable v ddi if needed. when the processor takes a sleep interrupt to wake up, the following steps should be taken: 1) after the sleep interrupt is taken, the pwr_en signal is asserted by hardware. within the time indicated by sys_powerctrl [vput], the system must ensure that v ddi is stable. 2) the processor will then boot from physical address 0x1fc0_0000 as normal. 3) if sleep is to be used by the system and a differ ent flow should be followed when coming out of sleep the sys_wakesrc should be read to determine if the processor is coming out of sleep and what caused the wakeup. the system should then write the sys_wakesrc register to clear this information. 4) the processor will need to perform complete system initializ ation. all registers except those described as otherwise in the system control block will be at their default values. programmable counters (toy and rtc) sys_cntrctrl if both the toy and rtc are no t being used, then disable the oscillator. ac97 controller ac97_enable if the ac97 block is not in use, the d bit should be used to disable the module and the ce bit should be disabled to gate clocks from the block. i 2 s i2s_enable if the i 2 s block is not in use, the e bit should be used to place the block in reset and the ce bit should be disabled to gate clocks from the block. table 7-6. peripheral power management (continued) peripheral power management register power management strategy
amd alchemy? au1000? processor data book - preliminary 191 power management 30360d 7.4.3.1 sleep sequence and timing as the processor enters sleep mode, the system designer has the option of disabling v ddi to conserve power. the pwr_en signal defines the sleep window. figure 7-7 shows the sleep sequence. figure 7-7. sleep sequence the system designer must ensure v ddi is stable from the rising edge of pwr_en within the time period as programmed in sys_powerctrl [vput]. note that vddxok (not shown) remains asserted during the sleep sequence. 7.4.4 power management registers the power management registers and their associated offsets are listed in table 7-7. these registers are located off of the base shown in table 7-1. 7.4.4.1 scratch registers the scratch registers keep their values through sleep and r untime resets. these registers allow the system programmer to save user-defined state information or a pointer to a context so that the previous context can be restored when coming out of sleep, if needed. note that the scratch registers have unpredictable default values after a hardware reset. table 7-7. power management registers offset from 0x0_1190_0000 (physical) 0x_b190_0000 (kseg1) register name description reset type 0x0018 sys_scratch0 user-defined register that retains its value through sleep. hardware 0x001c sys_scratch1 user-defined register that retains its value through sleep. hardware 0x0034 sys_wakemsk sets which gpio or whether toy match can cause sleep wakeup. hardware 0x0038 sys_endian sets big or little endian. hardware & runtime 0x003c sys_powerctrl sets system bus divider and power-up time. mixed - see register description 0x005c sys_wakesrc gives source of sleep wakeup. hardware 0x0078 sys_slppwr initiates power state for sleep mode. hardware 0x007c sys_sleep initiates sleep mode. hardware sys_scratch0 offset = 0x0018 sys_scratch1 offset = 0x001c bit313029282726252423222120191817161514131211109876543210 scratch[31:0] def.xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx bits name description r/w default 31:0 scratch user-defined information. r/w unpred pwr_en v ddi vput
192 amd alchemy? au1000? processor data book - preliminary power management 30360d 7.4.4.2 wakeup source mask register for each individual bit that is set, the corresponding signal or event (for the case of the toy match) can be used to cause a sleep wakeup. a high level on the enabled gpio will cause the interrupt to trigger. this register will reset to defaults only on a hardware reset. during a runtime reset and during sleep this register retains it s value. 7.4.4.3 endiann ess register to change the endianness of the au1000 processor is a three step process as follows: 1) program the endianness bit in the system endianness register ( sys_endian [en]). 2) read the sys_endian register. (this is required to ensure the fina l write to the cp0 register will update the endian value.) 3) read the cp0 register config0 . (see section 2.7.15 "configuration register 0 (cp0 register 16, select 0)" on page 34.) 4) write the value read back into the cp0 config0 register. the act of writing the cp 0 register will put the processor into the endian state as programmed in sys_endian [en]. this register as well as the processor endianness will reset to big endian after a hardware reset, runtime reset and after sleep. sys_wakemsk offset = 0x0034 bit313029282726252423222120191817161514131211109876543210 m2 gpio[7:0] def.00000000000000000000000000000000 bits name description r/w default 31:9 ? reserved. should be cleared. r 0 8 m2 setting this bit enables the programmable toy counter match register 2 ( sys_toymatch2 ) to cause a wakeup interrupt. see section 7.2.1.3 "match registers" on page 180. r/w 0 7:0 gpio[7:0] setting bit n causes gpio[ n ] to cause a sleep wakeup. r/w 0 sys_endian offset = 0x0038 bit313029282726252423222120191817161514131211109876543210 en def.xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx0 bits name description r/w default 31:1 ? reserved. should be cleared. r unpred 0 en endianness. 0 big endian 1 little endian r/w 0
amd alchemy? au1000? processor data book - preliminary 193 power management 30360d 7.4.4.4 power control register bits[6:5] of this register are reset to default val ues for a hardware reset, runtime reset and after sleep. bits[4:0] of this register reset to default values only on a hardware reset. during a runtime reset and during sleep these bits retain their values. 7.4.4.5 wakeup cause register before setting the sleep bit this register should be cleared. th is register will retain pending interrupts according to the set - ting in the sys_wakemsk register even if those events did not occur during sleep. in other words if a gpio?s functionality is multiplexed between multiple functions, a high level could cause the associated sys_wakesrc bit to be set even if the action did not occur during sleep. the bits in this register must be explicitly cleared as they will hold their values through sleep and a runtime reset. all bits in this register are set by hardware and cleared by any write to this register. sys_powerctrl offset = 0x003c bit313029282726252423222120191817161514131211109876543210 si sb vput sd def.00000000000000000000000000000000 bits name description r/w default 31:7 ? reserved. should be cleared. r 0 6 si idle state system bus clock divider enable. 0 the idle state system bus clock divider is disabled. 1 enable the system bus clock to be divided by an additional factor of 2 when the processor is in an idle state (taken through the wait instruc- tion). all peripheral bus clocks (such as the sdram and uart controllers) will be internally compensated with no programmer intervention required. note: sd must be programmed to 00 (divide by two) when si is set. r/w 0 5 sb system bus clock divider enable. 0 the system bus clock divider is disabled. 1 enable the system bus clock to be divided by an additional factor of 2 when there is no bus activity. all cl ocks derived from the peripheral bus clock (such as the sdram and uart c ontrollers) will be internally com- pensated with no programmer intervention required. note: sd must be programmed to 00 (divide by two) when sb is set. r/w 0 4 ? reserved. should be cleared. r 0 3:2 vput v ddi power-up time. 00 20 ms 01 5 ms 10 100 ms 11 2 s r/w hardware reset 00 1:0 sd system bus clock divider. 00 2 01 3 10 4 11 reserved r/w hardware reset 00 sys_wakesrc offset = 0x005c bit313029282726252423222120191817161514131211109876543210 m2 gp7 gp6 gp5 gp4 gp3 gp2 gp1 gp0 sw ip def.000000rs0000000000000000000000rs bits name description r/w default 31:25 ? reserved. should be cleared. r/w 0
194 amd alchemy? au1000? processor data book - preliminary power management 30360d 7.4.4.6 sleep power register 7.4.4.7 sleep register 24 m2 programmable toy match 2 caused wakeup from sleep. set by hardware on sleep wakeup due to toy match. cleared by hardware on vddxok assertion. this bit must be explicit ly cleared by software (any write) because it holds its value through sleep and runtime reset. r/w 0 23 gp7 gpio[ n ] caused wakeup from sleep. set by hardware on sleep wakeup due to gpio[ n ]. this bit must be explicit ly cleared by software (any write) because it holds its value through sleep and runtime reset. r/w 0 22 gp6 r/w 0 21 gp5 r/w 0 20 gp4 r/w 0 19 gp3 r/w 0 18 gp2 r/w 0 17 gp1 r/w 0 16 gp0 r/w 0 15:2 ? reserved, should be cleared. r/w 0 1 sw sleep wakeup. this bit is set by hardware on a sleep wakeup and cleared by software by a write to this register. a runtime reset can be detected if both sw and ip are 0 at boot. this bit must be explicit ly cleared by software (any write) because it holds its value through sleep and runtime reset. r/w 0 0 ip initial power-up. th is bit is set by hardware on a hardware reset and cleared by software by a write to this register. a runtime reset can be detected if both sw and ip are 0 at boot. this bit must be explicit ly cleared by software (any write) because it holds its value through sleep and runtime reset. r/w 1 sys_slppwr offset = 0x0078 bit313029282726252423222120191817161514131211109876543210 sp def.xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx bits name description r/w default 31:0 sp a write to this register prepares the internal power supply for going to sleep. w unpred sys_sleep offset = 0x007c bit313029282726252423222120191817161514131211109876543210 sl def.xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx bits name description r/w default 31:0 sl a write to this register puts system to sleep. w unpred bits name description r/w default
amd alchemy? au1000? processor data book - preliminary 195 power management 30360d
amd alchemy? au1000? processor data book - preliminary 196 8 power-up, reset and boot 30360d 8.0 power-up, reset and boot this section presents the power-up, hardware reset and runtim e reset sequence for the au1000 processor. in addition the boot vector is described. 8.1 power-up sequence the au1000 processor power structure is desi gned such that the external i/o voltage (v ddx ) is driven separately from the core voltage (v ddi ). in this way the core voltage can be sourced at lower voltages saving power. in addition the au1000 processor is designed to allow the system designer to remove the core voltage during sleep to maximize power efficiency. two signals vddxok and pwr_en are used to facilitate this power strategy. vddxok is used as a signal to the proces- sor that power on v ddx is stable. stable is defined as having reached 90 % of its nominal value. pwr_en is an output from the au1000 that is asserted after vddxok is asserted and can be used as an enable to the regulator that is providing the core voltage, v ddi . the following describes the power-up sequence for the au1000 processor: 1) apply v ddx (3.3v i/o power). 2) when v ddx has reached 90% of nominal, assert vddxok. 3) the au1000 processor then asserts pwr_en which can be used to enable the regulator driving vddi (cpu power). figure 8-1 shows the power-up sequence, including arrows re presenting causal dependencies. for the timing specifica- tions of this sequence, refer to section 11.5.1 "power-up sequence timing" on page 249. figure 8-1. power-up sequence 8.2 reset a hardware reset is defined as a reset in which both vddxok and resetin# are t oggled. typically th is happens only at power-on, but a system designer can choose to tie vddxok and resetin# together in which case all resets will be hard- ware resets. for a runtime reset, power remains applied and only the resetin # signal is toggled. note that certain registers, specifi- cally some of those in the system control bl ock, are not affected by this type of re set. see the register description for the register in question for more information. if a register is not reset to defaults by both hardware reset and runtime reset, it is noted in the register description. v ddx vddxok pwr_en v ddi
amd alchemy? au1000? processor data book - preliminary 197 power-up, reset and boot 30360d 8.2.1 hardware reset for a hardware reset, vddxok makes a transition from low to high followed by resetin# ne gating (transitioning from low to high). the following sequence describes a hardware reset: 1) romsel and romsize should be terminated in the design so the appropriate boot type occurs. these values should not change during runtime. 2) at the same time or after vddxok is asserted, r esetin# can be negated. in other words, resetin# can not be negated before vddxok is asserted. this allows vddxok and r esetin# to be ti ed together. 3) resetout# is negated after resetin# is negated. figure 8-2 shows the hardware reset sequence, including arro ws representing causal dependenc ies. for the timing specifi- cations of this sequence, refer to section 11.5.2 "hardware reset timing" on page 250. figure 8-2. hardware reset sequence 8.2.2 runtime reset during runtime (after power is stable) the reset sequence can be broken down as follows: 1) during a runtime reset it is assumed that v ddx and v ddi remain at their nominal volt age. in addition, vddxok must remain asserted; otherwise, a hardware reset will occur. pwr_en remains asserted by the au1000 processor. 2) resetin# is held asserted long enough to be recognized as a valid reset. 3) the processor acknowledges the reset by asserting resetout#. 4) after resetin# is released, th e processor signals the end of the reset by negating resetout#. note that certain regi sters (specifically those in the system control block) are not affect ed by a runtime reset. note also tha t romsel and romsize should already be terminated in the design so the appropriate boot type occurs?these values should not change during runtime. figure 8-3 shows the runtime reset sequence, including arrows representing causal dependenc ies. for the timing specifi- cations of this sequence, refer to section 11.5.3 "runtime reset timing" on page 251. figure 8-3. runtime reset sequence vddxok resetin# resetout# v ddx (at nominal voltage) vddxok (asserted high) pwr_en (remains asserted) v ddi (at nominal voltage) resetin# resetout#
198 amd alchemy? au1000? processor data book - preliminary power-up, reset and boot 30360d 8.3 boot for both hardware and runtime resets, the cpu boots from kseg1 address 0x_bfc0_0000 whic h is translated to physical address 0x0_1fc0_0000; therefore, the system designer should place the start of the boot code at 0x0_1fc0_0000. the romsel and romsize signals determine the boot device type and width according to table 8-1. the system designer should configure romsel and romsize appropriately. note that romsel and romsize should not change during runtime. rcs0# is configured to be enabled for 0x0_1fc0_0000 at default when booting from a rom device (romsel = 0, rom- size = x). see section 3.2 "static bus controller" on page 53, for more information about the default timing and size of the address enabled at reset. sdcs0# is configured to be enabled for 0x0_1fc0_0000 at default when booting from a smrom device (romsel = 1, romsize = 0). see section 3.1 "sdram memory controller" on page 44, for more information about the default timing and size of the address enabled at reset. 8.3.1 endianness and 16-bit static bus boot when booting from a 16-bit chip select on the static bus, the system designer must be sure the data format (endianness) is consistent across the au1 core, the static bus controller, an d the software image itself. this section describes how to make endianness consistent for both little- and bi g-endian systems. for more on how the endian mode affects the behavior of 16-bit static bus chip selects, see "halfword ordering and 16-bit chip selects" on page 71. note: when programming rom or flash devices with a part prog rammer, take care to ensure that the programmer is not swapping bytes or halfwords erroneously. the configur ation of the part programmer is often a source of error when initially bringing-up a new design. 8.3.1.1 16-bit boot fo r little-endian system booting from 16-bit rom or flash in a system that is intended to run the au1 core in little-endian mode is very straightfor- ward. generally speaking, the boot code and/or the applic ation is compiled for little-endian. because the the au1 core defaults to big-endian mode, the boot code must change the au1 core endianness to little-endian before any data accesses (to the 16-bit chip-select). the resulting bo ot code and/or application image is plac ed in the rom/flash memory in the little- endian format. even though the au1 core starts in big-endian mode, the stat ic bus controller properly retrieves instructions needed to boot the system since the application image is in little-endian format and the static bus controller defaults to little-endian order ing out of reset. table 8-1. romsel and romsize boot device romsel romsize boot device type and width 0 0 boot from 32-bit rom interface 0 1 boot from 16-bit rom interface 1 0 boot from 32-bit smrom interface and sync flash boot 11reserved
amd alchemy? au1000? processor data book - preliminary 199 power-up, reset and boot 30360d 8.3.1.2 16-bit boot for big-endian system booting from 16-bit rom or flash in a system that is intended to run th e au1 core in big-endian mode is very straightforard, but does need one extra, important step. generally speaking, the boot c ode and/or the application is compiled for big-endian. the boot code must set the mem_stcfg [be] bit before it can properly fetch/reference the bi g-endian image. the resulting boot code and/or application image is placed in the rom/flash memory in the big-endian format. in this situation, there is the dilema t hat, out of reset, the static bus controller defaults to little-endian ordering, but th e appli- cation image itself is in big-endian format. the solution is to place the following code at the reset exception vector (kseg1 address 0x_bfc0_0000, physical adddress 0x0_1fc0_0000): .long 0xb4003c08 # lui t0,0xb400 .long 0x10003508 # ori t0,t0,0x1000 .long 0x00008d09 # lw t1,0(t0) .long 0x02003529 # ori t1,t1,0x200 .long 0x0000ad09 # sw t1,0(t0) .long 0x00000000 # nop .long 0x00000000 # nop .long 0x00000000 # nop .long 0x00000000 # nop the code does a read-modify-write of register mem_stcfg0 to set the be bit. the values in the .long statements above are the halfword-swapped opcodes of the instruct ions in the comments to the right. with this technique, these first few instruc- tions are actually in the little-end ian format to match the static bu s controller out of reset, and set mem_stcfg [be] which in turns allows the remainder of the big-endian memory contents to be accessed properly. the nops are necessary to ensure that the au1 core pipeline does not contain incorrectly [halfw ord swapped] prefetched instructions. note too that the nop opcode 0x00000000 is the same instruction regardless of endian ordering. note: the boot code should set mem_stcfg0 [be] as early as possible, preferrably as the first activity. it is especially important to ensure that no cachable accesses take place to the 16-bit device, else the cache will contain the half- word swapped contents of the 16-bit memory. 8.3.2 system boot for system debug, the processor can be configured to boot from the ejtag pro be through the ejtag port; see section 9.0 "ejtag" on page 200 for more information.
amd alchemy? au1000? processor data book - preliminary 200 9 ejtag 30360d 9.0 ejtag the au1000 processor implements ejtag following the mips? ejtag 2.5 specification. this section presents the ejtag implementation on the au1000 processor while concentrating on those features from the ej tag 2.5 specification which are implementation specific. in addition, those features which have not been implemented or any differences in the au1000 processor implementation of ejtag from t he rev 2.5 specification are also noted. it is assumed that the ejtag 2.5 specification will be referenc ed for implementation details not covered here. if a particular bit is not implemented it can be assumed that the functional ity associated with the bit is not implemented or not applicable unless otherwise noted. the following features comprise the ejta g implementation on the au1000 processor: extended instructions sdbbp and deret debug exceptions extended cp0 registers debug, depc and desave ejtag memory range 0xff200000 - 0xff3fffff instruction/data breakpoints through the watch exception (specific to au1000) processor bus breakpoints (from ejtag 2.0) memory overlay (from ejtag 2.0) ejtag tap per ieee1149.1 note: the optional data and instruction breakpoint features from the ejtag 2.5 specific ation are not implemented. 9.1 ejtag instructions both sdbbp and deret are supported by the au1000 processor: sdbbp causes a debug breakpoint exception. deret is used to return from a debug exception. 9.2 debug exceptions the following exceptions will cause entry into debug mode. dss - debug single step dint - debug interrupt, processor bus break dbp - execution of sdbbp instruction dwatch - debug watch exception. au1000 processor-specif ic implementation allowing cpu watch exception to cause debug exception. see description of the ?ejwatch register (tap instruct ion ejwatch)? on page 214 register. note that other normal exceptions, when taken in debug mode, are handled by the debug exception handler.
amd alchemy? au1000? processor data book - preliminary 201 ejtag 30360d 9.3 coprocessor 0 registers the coprocessor 0 registers for ejtag are shown in table 9-1. 9.3.1 debug register (cp0 register 23, select 0) the debug register contains the cause of the most recent debug exception and exception in debug mode. it also controls single stepping. only the dm bit and the ejtagver field ar e valid when read from the debug register in non-debug mode; the value of all other bits and fields is unpredictable. the following bits and fields are updated only on de bug exceptions and/or exceptions in debug mode: dss, dbp, dint are updated on both debug e xceptions and on exceptions in debug modes. dexccode is updated on normal exceptions in debug mode, and is undefined after a debug exception. dbd is updated on both debug and on normal exceptions in debug modes. table 9-1. coprocessor 0 registers for ejtag register number select name description 23 0 debug debug indications and controls for the processor 24 0 depc program counter at last debug exception or exception in debug mode 31 0 desave debug exception save register debug cp0 register 23, select 0 bit313029282726252423222120191817161514131211109876543210 dd dm nd ls cd ver dexcose ns ss di db ds def.x0000000000000001 xxxxx 0000x000xx bits name description r/w default 31 dd dbd. indicates whether the last debug exception or exception in debug mode occurred in a branch or jump delay slot. 0 not in delay slot. 1 in delay slot. r unpred 30 dm indicates that the processor is operating in debug mode. 0 processor is operating in non-debug mode. 1 processor is operating in debug mode. r0 29 nd nodcr. 0 dseg is present. 1 dseg is not present. r0 28 ls lsnm. controls access of loads/stores between dseg and remaining memory when dseg is present and while in debug mode. 0 loads/stores in dseg address range go to dseg. 1 loads/stores in dseg address range go to system memory. r/w 0 27 ? reserved. should be cleared. this bit is called doze in the ejtag 2.5 specification and is not implemented . r0 26 ? reserved. should be cleared. this bit is called halt in the ejtag 2.5 specification and is not implemented . r0 25 cd countdm. this bit is 0, indicating that the counter will be stopped in debug mode. r0 24 ? reserved. should be cleared. this bit is called ib usep in the ejtag 2.5 specification and is not implemented . r0 23 ? reserved. should be cleared. this bit is called mcheckp in the ejtag 2.5 specification and is not implemented . r0
202 amd alchemy? au1000? processor data book - preliminary ejtag 30360d 22 ? reserved. should be cleared. this bit is called cacheep in the ejtag 2.5 specification and is not implemented . r0 21 ? reserved. should be cleared. this bit is called dbusep in the ejtag 2.5 specification and is not implemented . r0 20 ? reserved. should be cleared. this bit is called iexi in the ejtag 2.5 specification and is not implemented . r0 19 ? reserved. should be cleared. this bit is called ddbsimpr in the ejtag 2.5 specification and is not implemented . r0 18 ? reserved. should be cleared. this bit is called ddblimpr in the ejtag 2.5 specification and is not implemented . r0 17:15 ver ejtagver. 1 ejtag version 2.5 r1 14:10 dexcode dexccode. indicates the cause of the latest exception in debug mode. the field is encoded as t he exccode field in the cause register for those exceptions that can occur in debug mode (the encoding is shown in the mips32 specification), with addit ion of code 30 with the mnemonic cacheerr for cache errors. this value is undefined after a debug exception. r unpred 9 ns nosst. 0 single step is implemented. 1 single step is not implemented. r0 8 ss sst. controls whether single-step feature is enabled: 0 no enable of single-step feature 1 single-step feature enabled r/w 0 7:6 ? reserved. should be cleared. r 0 5 di dint. indicates that a debug interrupt exception occurred. this could be either a processor bus break (indica ted by bs0 in the processor bus break status register) or ejtag brea k. the bs0 bit should be checked to see what caused the exception. cleared on exception in debug mode. 0 no debug interrupt exception 1 debug interrupt exception r unpred 4 ? reserved. should be cleared. this bit is called dib in the ejtag 2.5 spec- ification and is not implemented . r0 3 ? reserved. should be cleared. this bit is called ddbs in the ejtag 2.5 specification and is not implemented . r0 2 ? reserved. should be cleared. this bit is called ddbl in the ejtag 2.5 specification and is not implemented . r0 1 db dbp. indicates that a debug breakpoint exception occurred. cleared on exception in debug mode. 0 no debug breakpoint exception. 1 debug breakpoint exception. r unpred 0 ds dss. indicates that a debug singl e step exception occurred. cleared on exception in debug mode. 0 no debug single-step exception. 1 debug single-step exception. r unpred bits name description r/w default
amd alchemy? au1000? processor data book - preliminary 203 ejtag 30360d 9.3.2 debug exception program counter register the debug exception program counter (depc) register is a read/write register that contains the address at which process- ing resumes after the exception has been serviced. hardware updates this register on debug e xceptions and exceptions in debug mode. for precise debug exceptions and pr ecise exceptions in debug mode, t he depc register contains either: the virtual address of the instruction that was the direct cause of the exception; or the virtual address of the immediately preceding branch or jump instruction, when the exception-causing instruction is in a branch delay slot, and the debug branch delay (bdb) bit in the debug register is set. for imprecise debug exceptions and impr ecise exceptions in debug mode, the d epc register contains the address at which execution is resumed when returning to non-debug mode. 9.3.3 debug exception save register - desave the debug exception save (desave) register is a read/write register that functions as a simple scratchpad register. the debug exception handler uses this to save one of the gprs, which is then used to save the rest of the context to a pre- determined memory area, for example, in the dmseg. this regi ster allows the safe debugging of exception handlers and other types of code where the existence of a va lid stack for context saving cannot be assumed. 9.4 ejtag memory range in debug mode accesses to virtual 0x_ff20_0000 to 0x_ff3f_ffff bypass translation. the debug memory is split into two logical divisions: dmseg: 0x_ff20_0000 to 0x_ff2f_ffff drseg: 0x_ff3_0000 to 0x_ff3f_ffff note that the physical address addr(35:32) of this range is zero. dmseg is the memory range that will be serv iced by the probe tap in debug mode for all instruction accesses to this virtual address range and for data accesses if the lsnm in the debug register is 0. drseg is the memory range containing the ejtag memory mapped registers and is accessible when lsnm in the debug register is 0. depc - debug exception program counter cp0 register 24, select 0 bit313029282726252423222120191817161514131211109876543210 depc[31:0] def.00000000000000000000000000000000 bits name description r/w default 31:0 depc debug exception program counter. r/w unpred desave - debug exception save register cp0 register 31, select 0 bit313029282726252423222120191817161514131211109876543210 desave[31:0] def.xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx bits name description r/w default 31:0 desave debug exception save contents. r/w unpred
204 amd alchemy? au1000? processor data book - preliminary ejtag 30360d 9.4.1 ejtag memory mapped registers table 9-2 shows the ejtag memory m apped registers located in drseg. the ejtag implementation in the au1000 processor does not employ data breakpoints a nd instruction breakpoints as described in the ejtag 2.5 specification. instead it offers pr ocessor breakpoints as described in the ejtag 2.0.0 specifi- cation. the processor bus match registers monitor the bus interface of the mips cpu and provide debug exception or trace trig- ger for a given physical address and data. in addition, the implementation allows the cpu watchpoints to cause a debug exception. this functionality is enabled through the ejtag tap port. please see ?ejwatch register (tap instruction ejwatch)? on page 214 for details. 9.4.1.1 debug control register the debug control register (dcr) controls and provides info rmation about debug issues. the width of the register is 32 bits. the dcr is located in the drseg at offset 0x0000. table 9-2. ejtag memory mapped registers at 0x_ff30_0000 offset register description 0x0000 dcr debug control register 0x000c pbs processor break status 0x0300 pab processor address bus break 0x0304 pdb processor data break 0x0308 pdm processor data mask 0x030c pbcam processor control/address mask 0x0310 phab processor high address break 0x0314 pham processor high address mask dcr - debug control register offset = 0x0000 bit313029282726252423222120191817161514131211109876543210 en db ib ie ne np sr pe def.00100000000000000000000000011010 bits name description r/w default 31:30 ? reserved. should be cleared. r 0 29 en enm. 1 processor is big endian in both debug and kernel mode. r1 28:18 ? reserved. should be cleared. r 0 17 db databrk. 0 no data hardware breakpoints implemented. r0 16 ib instbrk. 0 no instruction hardwar e breakpoints implemented. r0 15:5 ? reserved. should be cleared. r 0 4ie inte. 1 interrupt enabled in debug mode depending on other enabling mech- anisms. r1 3ne nmie. 1 non-maskable interrupt is enable for non-debug mode. the nmi is not implemented in the a u1000 so this bit has no applicability. r1
amd alchemy? au1000? processor data book - preliminary 205 ejtag 30360d 9.4.1.2 processor bus br eak status register 9.4.1.3 processor address bus break this register contains the bits of the physical processor address bus break. 2 np nmipend. 0 no nmi pending the nmi is not implemented in the a u1000 so this bit has no applicability. r0 1sr srste. 1 soft reset is fully enabled. soft reset is not implemented in the au1000 so this bit has no applicabil- ity. r1 0 pe proben. indicates value of the proben value in the ecr register. 0 no access should occur to dmseg 1 probe services accesses to dmseg r same value as proben in ecr pbs - processor bus break status offset = 0x000c bit313029282726252423222120191817161514131211109876543210 olp bcn bs def.01000001000000000000000000000000 bits name description r/w default 31 ? reserved. should be cleared. r 0 30 olp 1 memory overlay functionality is implemented for processor breaks. r 1 29:28 ? reserved. should be cleared. r 0 27:24 bcn number of processor breaks. 1 one channel has been implemented for the processor bus break. r1 23:15 ? reserved. should be cleared. r 0 14:1 ? reserved. should be cleared. these bits are the bsn bits in the ejtag 2.0.0 specification and are not needed since only one break is imple- mented. r0 0 bs break status. this bit, when set, i ndicates that a processor bus break or processor bus trigger has occurred. bs can be cleared by activating prrst (ejtag control register), hard reset and also by writing a ?0? to it. the debug handler must clear this bit before returning from debug mode. r/w 0 pab - processor address bus break offset = 0x0300 bit313029282726252423222120191817161514131211109876543210 pab[31:0] def.xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx bits name description r/w default 31:0 pab processor address bus break 0. this index contains the lower 32 bits of the physical address. in combinati on with the high order address bits, these bits make up the break address. r unpred bits name description r/w default
206 amd alchemy? au1000? processor data book - preliminary ejtag 30360d 9.4.1.4 processor data bus break this register specifies the data value for the processor data bus match. 9.4.1.5 processor data mask/u pper overlay address mask this register is dual purpose depending on the value of the overlay enable bit in the bus break control and address mask. this register specifies the mask value for the processor data mask register. each bit corresponds to a bit in the data regis- ter. 9.4.1.6 processor bus break control and address mask this register selects the processor bus matc h function to enable debug break or trace trigger. it also includes control bits to enable comparison as well as mask bits to exclude address bits from comparison. note that all processor brea k exceptions are imprecise. pdb - processor data bus break offset = 0x0304 bit313029282726252423222120191817161514131211109876543210 pdb[31:0] def.xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx bits name description r/w default 31:0 pdb processor data bus break 0. this index contains the 32 bits of the data bus match. r unpred pdm_uoam - processor data mask offset = 0x0308 bit313029282726252423222120191817161514131211109876543210 pdm[31:0] def.xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx bits name description r/w default 31:0 pdm processor data mask 0. when oe in the pbcam register is not enabled. 0 data bit is not masked, data bit is compared. 1 data bit is masked, data bit is not compared. note: applies only when oe not enabled. r unpred 31:24 uoam upper overlay address mask. t hese bits represent bits 31:24 of the address mask and are combined with the lam and ham fields to create a complete 36 bit address mask. 0 address bit is not masked, address bit is compared. 1 address bit is masked, address bit is not compared. bits 23:0 are not used when oe is set and should be written 0. note: applies only when oe is enabled. r/w unpred pbcam - bus break control and address mask offset = 0x030c bit313029282726252423222120191817161514131211109876543210 lam[31:8] dc du diu oe be def.xxxxxxxxxxxxxxxxxxxxxxxxxxxx 0000 bits name description r/w default 31:8 lam address mask. these bi ts specify the mask value for the 24 lower bits of the processor address register (pba0[ 23..0]). each bit corresponds to the same bit in pba0. 0 address bit is not masked, address bit is compared. 1 address bit is masked, address bit is not compared. r/w unpred
amd alchemy? au1000? processor data book - preliminary 207 ejtag 30360d 7 dc data store to cached area. this bit enables the comparison on processor address and data bus for data store to the cached area. 0 processor address and data is not compared for storing data to the cached area. 1 processor address and data is compared for storing data to the cached area. r/w unpred 6 du data store to uncached area. this bit enables the comparison on pro- cessor address and data bus for data store to the uncached area. 0 processor address and data is not compared for storing data into the un-cached area. 1 processor address and data is compared for storing data into the un- cached area. r/w unpred 5:4 diu data or instruction fetch or lo ad from uncached area. these bits enable the comparison on processor address and data bus for data or instruc- tion load and fetch from the un-cached area. 00 processor address and data is not compared for loading data or fetching instruction from the un-cached area. 11 processor address and data is compared for loading data or fetching instruction from the un-cached area. bits 5 and 4 were named iluc and dfuc in the ejtag 2.0.0 specification and were implemented separately for instruction and data fetches. r unpred 3 oe overlay enable. when this bit is 1 and the processor physical address, masked by the ham, uoam and the lam fields (all 36 bits of the address mask), matches the phab and pab registers, then the memory request is redirected to the ejtag probe. the processor bus break can not be us ed for normal break, function if the ole bit is set, so be must be set to 0. the behavior is otherwise unde- fined. overlay is only valid for memory regions. it is not valid for i/o or debug space and the behavior is unpredictable if addresses within this space are used. r/w 0 2 ? reserved. should be cleared. this bit is called te in the ejtag 2.0.0 specification and is not implemented . r0 1 ? reserved. should be cleared. this bit is called cbe in the ejtag 2.0.0 specification and is not implemented . r0 0 be break enable. this bit enables the processor bus break function. 0 processor bus break function is disabled. 1 processor bus break function is enabled. if break enable is set and the proces sor physical address, masked by the ham and the lam fields (uoam is only for overlay so bits 31:24 are not masked here), matches the phab and pab registers, and the processor data bus matches the pdb register (masked by pdm), then a debug exception to the processor is generated. the bs bit in the processor bus break st atus register is set and the dint bit in the debug register is set. if the debug exception handler is already running (dm=?1?), then the debug exception will not be taken until dm = 0. this functionality is mutually exclus ive to ole so only one of ole or be should be set at any time. r/w 0 bits name description r/w default
208 amd alchemy? au1000? processor data book - preliminary ejtag 30360d 9.4.1.7 processor high address bus break this register specifies the high order add ress for the processor address bus break. 9.4.1.8 processor high address mask this register specifies the high order address mask for the processor address bus break. pha - processor high address bus break offset = 0x0310 bit313029282726252423222120191817161514131211109876543210 ha[3:0] def.0000000000000000000000000000 xxxx bits name description r/w default 31:4 ? reserved. should be cleared. r 0 3:0 ha these bits map to the high phys ical address bits 35:31. r/w unpred pham - processor high address mask offset = 0x0314 bit313029282726252423222120191817161514131211109876543210 ham[3:0] def.0000000000000000000000000000 xxxx bits name description r/w default 31:4 ? reserved. should be cleared. r 0 3:0 ham high address mask for address bits 35:31. 0 data bit is not masked, data bit is compared 1 data bit is masked, data bit is not compared r/w unpred
amd alchemy? au1000? processor data book - preliminary 209 ejtag 30360d 9.4.2 ejtag test access port (tap) the ejtag tap contains the 5 tap pins and a 16 st ate controller with a 5 bit instruction register. table 9-3 shows the 5-bit instru ctions supported by the au1000. 9.4.2.1 device identifi cation (id) register the device id register is a 32-bit read-only register that identifies the specific device implementing ejtag. table 9-3. ejtag instruction register values hex value instruction function 0x00 extest boundary scan. 0x01 idcode selects id register. 0x02 sample boundary scan sample/preload (ieee jtag instruction). 0x03 impcode selects implementation register. 0x04 ? reserved. 0x05 ? this reserved register is for test mode hiz - tri-state all output pins and select bypass register. 0x06 ? this reserved register is for te st mode clamp - ieee clamp pins and select bypass register. 0x07 ? reserved. 0x08 address selects address register. 0x09 data selects data register. 0x0a control selects ejtag control register. 0x0b all selects the address, data and ejtag control registers. 0x0c ejtagboot makes the processor take a debug exception after reset. 0x0d normalboot makes the processor ex ecute the reset handler after reset. 0x0e-0x1b ? reserved. 0x1c ejwatch selects watch register. 0x1d-0x1e ? reserved. 0x1f bypass bypass mode. idcode - device identification tap instruction idcode bit313029282726252423222120191817161514131211109876543210 ver pnum manid def.00000000001111101000001010001111 bits name description r/w default 31:28 ver identifies the version of the device. r 0 27:12 pnum identifies the part number of the device. r 0x03e8 11:1 manid identifies the manufacturer id code for the device. manid[6:0] are derived from the last byte of the jedec code with the parity bit discarded. manid[10:7] provides a binary count of the number of bytes in the jedec code that contain the continuation character (0x7f). when the number of continuations characters exceeds 15, these four bits contain the modulo- 16 count. r0x147 0 ? reserved. should be written a 1. r 1
210 amd alchemy? au1000? processor data book - preliminary ejtag 30360d 9.4.2.2 implementation register the implementation register is a 32-bit re ad-only register that identifies features implemented in this ejtag compliant pro- cessor, mainly those accessible from the tap. 9.4.2.3 data register the read/write data register is used for opcode and data transf ers during processor accesses. the width of the data regis- ter is 32 bits. the value read in the data register is valid only if a processo r access for a write is pending, in which case the data register holds the store value. the value written to the data register is only used if a processor access for a pending read is finished afterwards, in which case the data value written is the value fo r the fetch or load. this behavior implies that the data regis- ter is not a memory location where a previously written value can be read afterwards. impcode - implementation tap instruction impcode bit313029282726252423222120191817161514131211109876543210 ver r3 di as m16 nd m32 def.00100000010000000100000000000000 bits name description r/w default 31:29 ejtagver 1 ejtag version 2.5 r 1 28 r3 0 r3k privileged environment. r 0 27:25 ? reserved. should be cleared. r 0 24 di 0 dint signal from the probe is not supported. r 0 23 ? reserved. should be cleared. r 0 22:21 as 10 8-bit asid. r 10 20:17 ? reserved. should be cleared. r 0 16 m16 0 no mips16 support. r 0 15 ? reserved. should be cleared. r 0 14 nd 1 no ejtag dma support r 1 13:1 ? reserved. should be cleared. r 0 0 mips32/64 0 32-bit processor. r 0 data tap instruction data or all bit313029282726252423222120191817161514131211109876543210 data[31:0] def.xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx bits name description r/w default 31:0 data data used by processor access. r/w unpred
amd alchemy? au1000? processor data book - preliminary 211 ejtag 30360d 9.4.2.4 address register the read-only address register provides the address for a processor access. the width of the register is 36 bits. the value read in the register is valid if a processor acce ss is pending, otherwise the val ue is undefined. the two lsbs of the register are used with the psz field fr om the ejtag control register to indicate the size and data position of the pending processor access transfer. these bits are not taken directly from the address referenced by the load/store (i.e. these bits are encoded with psz). 9.4.2.5 ejtag cont rol register (ecr) the 32-bit ejtag control register (ecr) handles processor reset, debug mode indication, access start, finish, and size and read/write indication. the ecr also: controls debug vector location and indication of serviced processor accesses. allows debug interrupt request. indicates processor low-power mode. the ejtag control register is not updated/written in the updat e-dr state unless the reset occurred; that is ro (bit 31) is either already 0 or is written to 0 at the same time. this condition ensures proper handling of processor accesses after a reset. bits that are r/w in the register return their written value on a subsequent read , unless other behavior is defined. internal synchronization hardware thus ensures that a written value is updated for reading immediately afterwards, even when the tap controller takes the shortest path from the update-dr to capture-dr state. note: to ensure a write is successful to the pe, pt and eb bits when the processor is undergoing a clock change (for pll lock/relock), the host must continue writing these bits until the write is verified by reading the change. failure to do this could result in the write of these bits being lost. reset of the processor can be indicated in the tck domain a number of tck cycles after it is removed in the processor clock domain in order to allow for proper synchronization between the two clock domains. address tap instruction address or all bit3534333231302928272625242322212019181716151413121110 9 8 7 6 5 4 3 2 1 0 address[36:0] def.xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx bits name description r/w default 35:0 address address used by processor access r unpred ecr - ejtag control register tap instruction control or all bit313029282726252423222120191817161514131211109876543210 ro psz dz prw pa pr pe pt eb dm def.1xx000000000x0000000000000000000 bits name description r/w default 31 ro indicates if a processor reset has occurred since the bit was cleared: 0 no reset occurred. 1 reset occurred. the ro bit stays set as long as reset is applied. this bit must be cleared to acknowledge that the reset was detected. the ejtag control register is not updated in the update-dr state unless ro is 0 or written to 0 at the same time. this is in order to ensure correct han- dling of the processor access after reset. r/w0 1
212 amd alchemy? au1000? processor data book - preliminary ejtag 30360d 30:29 psz indicates the size of a pending proc essor access, in combination with the address register. 00 byte 01 halfword 10 word 11 triple this field is valid only when a processor access is pending; otherwise, the read value is undefined. r unpred 28:23 ? reserved. should be cleared. r 0 22 dz doze. indicates if the processor is in a wait state: 0 processor is not in a wait state. 1 processor is in a wait state. r0 21 ? reserved. should be cleared. this bit is called halt in the ejtag 2.0.0 specification and is not implemented . r0 20 ? reserved. should be cleared. this bit is called perrst in the ejtag 2.0.0 specification and is not implemented . r0 19 prw indicates read or write of a pending processor access. 0 read processor access, for a fetch/load access. 1 write processor access, for a store access. this value is defined only when a processor access is pending. r unpred 18 pa indicates a pending processor access and controls finishing of a pending processor access. when read: 0 no pending processor access. 1 pending processor access. a write of 0 finishes a processor ac cess if pending; otherwise operation of the processor is undefined if the bi t is written to 0 when no processor access is pending. a write of 1 is ignored. r/w0 0 17 ? reserved. should be cleared. r 0 16 pr controls the processor reset. 0 no processor reset applied. 1 processor reset applied. setting this bit to 1 will apply a proc essor reset. when this bit is read back it will always read a 0. note that startup latencies should be observed when applying reset. r/w 0 15 pe controls indication to the processor of whether the probe expects to han- dle accesses to ejtag memory thro ugh servicing of processor accesses. 0 probe does not service processor accesses. 1 probe will service processor accesses. the proben bit is reflected as a r ead-only bit in the debug control regis- ter (dcr) bit 0. when a read from this bit shows a c hange, the new value has taken effect in the dcr. this handshake mechanism ensures that the setting from the tck clock domain takes effect in the processor clock domain. however, a change of the proben prior to setting the ejtagbrk bit is ensured to affect execution of the debug handler due to the debug excep- tion. not all combinations of proben and probtrap are allowed. please see the previous note about writ ing this bit (in ?ejtag control register (ecr)? on page 211). r/w determined by ejtag- boot bits name description r/w default
amd alchemy? au1000? processor data book - preliminary 213 ejtag 30360d 14 pt controls location of the debug exception vector: 0 normal memory 0x_bfc0_0480 1 ejtag memory 0x_ff20_0200 when a read from this bit shows a c hange, the new value has taken effect in the dcr. this handshake mechanism ensures that the setting from the tck clock domain takes effect in the processor clock domain. however, a change of the probtrap prior to setting the ejtagbrk bit is ensured to affect execution of the debug handler due to the debug excep- tion. not all combinations of proben and probtrap are allowed. please see the previous note about writ ing this bit (in ?ejtag control register (ecr)? on page 211). r/w determined by ejtag- boot 13 ? reserved. should be cleared. r 0 12 eb requests a debug interrupt exception to the processor when this bit is writ- ten as 1. this bit is cleared by har dware when the processor enters debug mode. if software then sets eb while the processor is already in debug, the request is not ignored but is delayed. that is, once the processor returns to normal mode, the pending debug exception request immediately sends the processor back into debug. a write of 0 is ignored. the debug request restarts the processor clock if the processor was in a wait mode, which stopped the processor clock. the read value indicates a pending debu g interrupt exception requested through this bit: 0 no pending debug interrupt exception requested through this bit 1 pending debug interrupt exception the read value can, but is not requi red to, indicate other pending dint debug requests (for example, through the dint signal). please see the previous note about writ ing this bit (in ?ejtag control register (ecr)? on page 211). r/w1 determined by ejtag- boot 11:4 ? reserved. should be cleared r 0 3 dm indicates if the processor is in debug mode: 0 processor is in non-debug mode. 1 processor is in debug mode. r0 2:0 ? reserved. should be cleared. r 0 bits name description r/w default
214 amd alchemy? au1000? processor data book - preliminary ejtag 30360d 9.4.2.6 ejwatch register (tap instruction ejwatch) the ejwatch register is used to enable cpu watchpoints to cause a debug exception. this functionality is unique to the au1000. 9.4.2.7 bypass re gister (tap instruction bypass) the bypass register is a one-bit read-onl y register, which provides a minimum shift path through the tap. this register is also defined in ieee 1149.1. ejwatch tap instruction ejwatch bit76543210 watch def.00000000 bits name description r/w default 7:3 ? reserved. should be cleared. r 0 2 ? reserved. should be cleared. this bit is the global scan test bit. r 0 1 ? reserved. should be cleared. this bit is a test mode bit. r 0 0 watch this bit controls the debug functionality of the cpu watch register. 0 normal watch exception mode. 1 debug watch exception mode . blocks writes to watch register in non-debug mode watch exception will become deb ug exceptions with dexcode=23 the pc will be saved in the depc (not in the epc as with a normal watch exception). note that the status, cause, and epc will not be affected by a debug watch exception when this bit is enabled. r/w 0 bypass tap instruction bypass bit 0 bp def. 0 bits name description r/w default 0 bp ignored on writes; returns zeros on reads. r 0
amd alchemy? au1000? processor data book - preliminary 215 ejtag 30360d 9.4.3 ejtag tap hardware considerations the ejtag interface consists of the signals listed in table 9-4. note that the ejtag tap signal tck must always be less than 1/4 the system bus clock speed for proper operation. in addition, termination as shown in ejtag 2.5 spec must be followed. table 9-4. ejtag signals signal input/output definition trst# i asynchronous tap reset tdi i test data input to the instruction or sele cted data registers. this signal will be sam- pled on the rising edge of tck tdo o test data output from the instruction or data register. this signal will transition on the falling edge (valid on rising edge) of tck tms i control signal for tap controller. this signal is sampled on the wising edge of tck. tck i control clock for updating tap controlle r and shifting data thr ough instruction or selected data register.
amd alchemy? au1000? processor data book - preliminary 216 10 signal descriptions 30360d 10.0 signal descriptions this section describes the external signals on the au1000 processor. in order to maximize the functionality of the au1000 processor, many of the pins have multiple uses. note that if a pin is configured for one use, any other functionality associated with th at pin can not be utilized at the same time. in other words a pin can not be used as a general-purpose i/o signal at the same time it is assigned to a peripheral device. (see section 7.3.1 "pin functionality" on page 183.) figure 10-1 shows the external signals of the au1000 processor. all signals are grouped according to their functional block. signals that share a pin are listed with the multiplexe d signal name in parentheses?the signal name shown in bold is the default. note: :a signal with an ?#? is active-low ; that is, the signal is considered as serted (active) when low and negated when high. active-high signals (no #) are considered asserted when high and negated when low.
amd alchemy? au1000? processor data book - preliminary 217 signal descriptions 30360d figure 10-1. au1000? processor external signals table 10-3 gives a description of all external signals on the au1000 processor. the signals have been grouped by func- tional block. signals that require external termination are noted in the description. table 10-3 also defines the default state of the signals during a hardware reset, a runtime reset, and sl eep. the abbreviations used for the signal types and the sig- nal states are defined in table 10-1 and table 10-2. sda[12:0] static bus controller sdba[1:0] sdd[31:0] sdqm[3:0]# sdras# sdcas# sdwe# sdclk[2:0] sdcs[2:0]# sdcke rad[31:0] rd[31:0] rben[3:0]# rwe# roe# rcs[3:0]# ewait# pce[2:1]# poe# pwe# pior# piow# pwait# preg# pios16# lclk lwait# lrd[1:0]# lwr[1:0]# usbh1p usbh1m usbdp (usbh0p) usbdm (usbh0m) s0clk (gpio[17]) s0din s0dout (gpio[16]) s0den (gpio[18]) s1clk ( acdo ) s1din ( acbclk ) s1dout ( acsync ) s1den ( acrst# ) irdatx (gpio[19]) irfirsel ( gpio[15] ) u1txd (gpio[21]) u1rxd u2txd (gpio[22]) u2rxd u3txd (gpio[23]) u3rxd u3cts ( gpio[9] ) u3dsr ( gpio[10] ) u3dcd ( gpio[11] ) u3ri ( gpio[12] ) u3rts ( gpio[13] ) u3dtr ( gpio[14] ) n0txclk n0txen n0txd[3:0] n0rxclk n0rxdv n0rxd[3:0] n0crs n0col n0mdc n0mdio n1txclk n1txen (gpio[24]) n1txd[3:0] (gpio[28:25]) n1rxclk n1rxdv n1rxd[3:0] n1crs n1col n1mdc n1mdio acsync (s1dout) acbclk (s1din) acdo (s1clk) acdi acrst# (s1den) trst# tdi tdo tms tck gpio[31:0] testen xti12 xto12 xti32 xto32 resetin# resetout# pwr_en vddxok v ddi [12:0], v ddx [25:0], v ss [35:0] tc[3:0] uart0 uart1 uart2 u0txd (gpio[20]) u0rxd uart3 mac0 mac1 gpio power mgmt. test & debug power clocks & reset usb host usb device ssi0 ssi1 irda ac97 pcmcia ac link mii ejtag lcd xpwr12, xagnd12 xpwr32, xagnd32 romsel romsize i2sclk (gpio[30]) i2sword (gpio[31]) i2sdi ( gpio[8] ) i2sdio (gpio[29]) i 2 s smromcke ( gpio[6] ) mii irdarx extclk[1:0] ( gpio[3:2] ) usbh0p ( usbdp ) usbh0m ( usbdm ) dma_req0 ( gpio[4] ) dma_req1 ( gpio[5] ) dma dma reqs sdram controller au1000? processor
218 amd alchemy? au1000? processor data book - preliminary signal descriptions 30360d note for table 10-3 that the signal states shown in the far-right column are valid during sleep. when waking from sleep, the processor performs an internal system reset t hat produces the same si gnal behavior as a runtime reset with two excep- tions: sdram interface behavior. during and after a runtime reset the sdram configuration mode registers retain their values to allow a transaction in progress to complete; the remaining sdram configuration registers revert to their default values. waking from sleep, however, all sdram configuration registers revert to their default values, and the interface behaves the same as when coming out of a hardware reset. pwr_en behavior. during a runtime reset pwr_en remains asserted. during sleep, pwr_en is negated. waking from sleep, pwr_en is asserted according to the timing specified in section 7.4.3.1 "sleep sequence and timing" on page 191. table 10-1. signal type abbreviations for table 10-3 signal type definition i input. note that all unused input pins should be terminated low or high via direct connection to either ground or power. o output io bidirectional z tristatable p power g ground table 10-2. signal state abbreviations for table 10-3 signal state definition 0 driven low 1 driven high in signal is a input. lv if driven, an output signal continues to be driven at the last value before a reset or entering sleep. hiz tri-state on clock remains on if already enabled . dep depends (signal-specific explanations are provided in table footnotes.) un unpredictable nc not connected na does not apply because this signal is not the default function coming out of a hardware or runtime reset.
amd alchemy? au1000? processor data book - preliminary 219 signal descriptions 30360d table 10-3. signal descriptions signal type description reset during sleep hardware run time sdram interface sda[12:0] o address outputs. a0-a12 are sampled during the active command (row-address a0-a12) and read / write command to select one location out of the memory array in the respective bank. the address outputs also provide the opcode during a load mode register command. un un lv sdba[1:0] o bank address output s. sdba1 and sdba0 define to which bank the active , read , write , or precharge command is being applied. un un lv sdd[31:0] io sdram data bus. during a hardware reset the sdram data bus cycles from low voltage to hi-z and then low as follows: 1. 0 after vddxok is asserted. 2. tri-state when v ddi is on and resetout# is asserted. 3. 0 after hardware reset sequence is complete. (see descrip- tion at left.) hiz lv sdqm[3:0]# o input/output mask: sd qm# is an input mask signal for write accesses and an output enable signal for read accesses. sdqm0# masks sdd[7:0]. sdqm1# masks sdd[15:8]. sdqm2# masks sdd[23:16]. sdqm33 masks sdd[31:24]. 11lv sdras# o command outputs. sdras#, sdcas#, and sdwe# (along with sdcsn#) define the command being sent to the sdram rank. 11lv sdcas# o 1 1 lv sdwe# o 1 1 lv sdclk[2:0] o clock output corresponding to each of the three chip selects. clock speed is 1/2 system bus frequency when corresponding sdcsn# is set to sdram, 1/4 system bus frequency when corresponding sdcsn# is set to smrom. 0onlv sdcs[2:0]# o programmable chip selects. 1 1 lv sdcke o clock enable for sdram. 0 1 lv smromcke o synchronous mask rom clock enable. valid only when romsel=1 and romsize=0. must be pulled high if the system is booting from smrom. muxed with gpio[6]. if romsel and romsize are configured to boot from synchronous mask rom, the smromcke signal is selected for the pin coming out of reset; otherwise, gpio[6] is selected. 11lv
220 amd alchemy? au1000? processor data book - preliminary signal descriptions 30360d static bus (sram/io/pcmcia/flash/r om/lcd) interface - common signals rad[31:0] o address bus. un un lv rd[31:0] io data bus 0 un lv rben[3:0]# o byte enable. rben0# corresponds to rd[7:0], rben1# corresponds to rd[15:8], rben2# corre- sponds to rd[23:16], rben3# corresponds to rd[31:24]. 11lv rwe# o write enable. 1 1 lv roe# o output enable. 1 1 lv rcs[3:0]# o programmable chip selects. rcsn# is not used when configured as a pcmcia device. 11lv ewait# i can be used to stretch the bus access time when enabled. this input is not recognized for chip selects configured as lcd or pcmcia because these buses have their own wait mechanisms. in in lv pcmcia preg# o register-only access signal. 1 1 lv pce[2:1]# o card enables. 1 1 lv poe# o output enable. 1 1 lv pwe# o write enable. 1 1 lv pior# o read cycle indication. 1 1 lv piow# o write cycle indication 1 1 lv pwait# extend cycle. this signal should be tied high through a resistor when the pcmcia interface is not used. in in lv pios16# 16-bit port select. this signal should be tied high through a resistor when the pcmcia interface is not used. in in lv lcd controller chip interface lclk o interface clock. 0 0 lv lwait# i extend cycle. this signal should be tied high through a resistor when not used. in in lv lrd[1:0]# o read indicators. 1 1 lv lwr[1:0]# o write indicators. 1 1 lv usb host usbh1p io positive signal of differential usb host port 1 driver. requires an external 15 kohm pull-down resistor and esd protection diode (transient voltage suppressor) to be usb 1.1 compliant. termination note: requires an external 27 ohm series resistor placed within 0.5 inches of the part. in in lv table 10-3. signal descriptions (continued) signal type description reset during sleep hardware run time
amd alchemy? au1000? processor data book - preliminary 221 signal descriptions 30360d usbh1m io negative signal of differential usb host port 1 driver. requires an external 15 kohm pull-down resistor and esd protection diode (transient voltage suppressor) to be usb 1.1 compliant. termination note: requires an external 27 ohm series resistor placed within 0.5 inches of the part. in in lv usbh0p io positive signal of differential usb host port 0 driver requires an external 15 kohm pull-down resistor and esd protection diode (transient voltage suppressor) to be usb 1.1 compliant. termination note: requires an external 27 ohm series resistor placed within 0.5 inches of the part. muxed with usbdp. usbdp is the default signal com- ing out of hardware reset, runtime reset, and sleep. na na lv usbh0m io negative signal of differential usb host port 0 driver requires an external 15 kohm pull-down resistor and esd protection diode (transient voltage suppressor) to be usb 1.1 compliant. termination note: requires an external 27 ohm series resistor placed within 0.5 inches of the part. muxed with usbdm. usbdm is the default signal coming out of hardware reset, runtime reset, and sleep. na na lv usb device usbdp io positive signal of differential usb device driver. requires a 1.5 kohm pull-up resistor to denote a full speed device. also requires an external esd protec- tion diode (transient voltage suppressor) to be usb 1.1 compliant. termination note: requires an external 27 ohm series resistor placed within 0.5 inches of the part. muxed with usbh0p. usbdp is the default signal coming out of hardware reset, runtime reset, and sleep. in in lv usbdm io negative signal of differential usb device driver. requires an external esd protection diode (transient voltage suppressor) to be usb 1.1 compliant. termination note: requires an external 27 ohm series resistor placed within 0.5 inches of the part. muxed with usbh0m. usbdm is the default signal coming out of hardware reset, runtime reset, and sleep in in lv table 10-3. signal descriptions (continued) signal type description reset during sleep hardware run time
222 amd alchemy? au1000? processor data book - preliminary signal descriptions 30360d ssi0 s0clk o master only clock output. the speed and polarity of clock edge is programmable. muxed with gpio[17]. s0clk is the default signal coming out of hardware reset, runtime reset, and sleep. 00lv s0din i serial data input. this signal may be tied to s0dout to create a single bidirectional data signal. in in lv s0dout o serial data output. this signal is in tri-state during a read and thus may be tied to s0din to create a sin- gle bidirectional data signal. muxed with gpio[16]. s0do ut is the default signal coming out of hardware reset, runtime reset, and sleep. 0unlv s0den o enable signal which frames transaction. the polarity is programmable. muxed with gpio[18]. s0de n is the default signal coming out of hardware reset, runtime reset, and sleep. 0unlv ssi1 s1clk o master only clock output. the speed and polarity of clock edge is programmable. muxed with acdo. acdo is the default signal coming out of hardware reset, runtime reset, and sleep. na na lv s1din i serial data input. this signal may be tied to s1dout to create a single bidirectional data signal. muxed with acbclk. acbclk is the default signal coming out of hardware reset, runtime reset, and sleep. na na lv s1dout o serial data output. this signal is in tri-state during a read and thus may be tied to s1din to create a sin- gle bidirectional data signal. muxed with acsync. acsync is the default signal coming out of hardware reset, runtime reset, and sleep. na na lv s1den o enable signal which frames transaction. the polarity is programmable. muxed with acrst#. acrst# is the default signal coming out of hardware reset, runtime reset, and sleep. na na lv irda irdatx o serial irda output. muxed with gpio[19]. irdatx is the default signal coming out of hardware reset, runt- ime reset, and sleep 0unlv irdarx i serial irda input. in in lv table 10-3. signal descriptions (continued) signal type description reset during sleep hardware run time
amd alchemy? au1000? processor data book - preliminary 223 signal descriptions 30360d irfirsel o output which will signal at which speed the irda is currently set. this signal is not necessary for irda operation. this pin will be driven high when irda is configured for fir or mir. this pin will be driven low for sir mode. muxed with gpio[15]. gpio[15] is the default signal coming out of hardware reset, runtime reset, and sleep. na na lv uart0 u0txd o uart0 transmit. muxed with gpio[20]. u0txd is the default signal coming out of hardware reset, runtime reset, and sleep. 0unlv u0rxd i uart0 receive. in in in uart1 u1txd o uart1 transmit. muxed with gpio[21]. u1txd is the default signal coming out of hardware reset, runtime reset, and sleep. 0unlv u1rxd i uart1 receive. in in in uart2 u2txd o uart2 transmit. muxed with gpio[22]. u2txd is the default signal coming out of hardware reset, runtime reset, and sleep. 0unlv u2rxd i uart2 receive. in in in uart3 u3txd o uart3 transmit. muxed with gpio[23]. u3txd is the default signal coming out of hardware reset, runtime reset, and sleep. 0unlv u3rxd i uart3 receive. in in in u3cts i clear to send. muxed with gpio[9]. gpio[9] is the default signal coming out of hardware reset, runtime reset, and sleep. system note : for systems that use the uart3 inter- face without the optional modem control signals ( sys_pinfunc [ur3]=0), the modem status interrupts must be disabled ( uart3_inten [mie]=0) to avoid false uart3 interrupts when us ing gpio[9], gpio[10], gpio[11], or gpio[12] as an input. na na lv u3dsr i data set ready. muxed with gpio[10]. gpio[10] is the default signal coming out of hardware reset, runt- ime reset, and sleep. system note : for systems that use the uart3 inter- face without the optional modem control signals ( sys_pinfunc [ur3]=0), the modem status interrupts must be disabled ( uart3_inten [mie]=0) to avoid false uart3 interrupts when us ing gpio[9], gpio[10], gpio[11], or gpio[12] as an input. na na lv table 10-3. signal descriptions (continued) signal type description reset during sleep hardware run time
224 amd alchemy? au1000? processor data book - preliminary signal descriptions 30360d u3dcd i data carrier detect. muxed with gpio[11]. gpio[11] is the default signal coming out of hardware reset, runtime reset, and sleep. system note : for systems that use the uart3 inter- face without the optional modem control signals ( sys_pinfunc [ur3]=0), the modem status interrupts must be disabled ( uart3_inten [mie]=0) to avoid false uart3 interrupts when us ing gpio[9], gpio[10], gpio[11], or gpio[12] as an input. na na lv u3ri i ring indication. muxed with gpio[12]. gpio[12] is the default signal coming out of hardware reset, runtime reset, and sleep. system note : for systems that use the uart3 inter- face without the optional modem control signals ( sys_pinfunc [ur3]=0), the modem status interrupts must be disabled ( uart3_inten [mie]=0) to avoid false uart3 interrupts when us ing gpio[9], gpio[10], gpio[11], or gpio[12] as an input. na na lv u3rts o request to send. muxed with gpio[13]. gpio[13] is the default signal coming out of hardware reset, runt- ime reset, and sleep. na na lv u3dtr o data terminal read y. muxed with gpio[14]. gpio[14] is the default signal coming out of hardware reset, runtime reset, and sleep. na na lv ethernet controller 0 n0txclk i continuous clock input for synchronization of transmit data. 25 mhz when operating at 100 mbps and 2.5 mhz when operating at 10 mbps. in in lv n0txen o indicates that the data ni bble on n0txd[3:0] is valid. 0 un lv n0txd[3:0] o nibble wide data bus synchronous to n0txclk. for each n0txclk period in which n0txen is asserted, txd[3:0] will have the data to be accepted by the phy. while n0txen is de-asserted the data pre- sented on txd[3:0] should be ignored. 0unlv n0rxclk i continuous clock that provides the timing reference for the data transfer from the phy to the mac. n0rxclk is sourced by the phy. the n0rxclk shall have a frequency equal to 25% of the data rate of the received signal data stream (typically 25 mhz at 100-mbps and 2.5 mhz at 10-mbps). in in lv n0rxdv i indicates that a receive frame is in process and that the data on n0rxd[3:0] is valid. in in lv n0rxd[3:0] i rxd[3:0] is a nibble wide data bus driven by the phy to the mac synchronous with n0rxclk. for each n0rxclk period in which n0rxdv is asserted, rxd[3:0] will transfer four bits of recovered data from the phy to the mac. while n0rxdv is de-asserted, rxd[3:0] will have no effect on the mac. in in lv table 10-3. signal descriptions (continued) signal type description reset during sleep hardware run time
amd alchemy? au1000? processor data book - preliminary 225 signal descriptions 30360d n0crs i n0crs shall be asserted by the phy when either transmit or receive medium is non idle. n0crs shall be deasserted by the phy when both the transmit and receive medium are idle. n0crs is an asynchronous input. in in lv n0col i n0col shall be asserted by the phy upon detection of a collision on the medium, and shall remain asserted while the collision condition persists. n0col is an asynchronous input. the n0col signal is ignored by the mac when operating in the full duplex mode. in in lv n0mdc o n0mdc is sourced by the mac to the phy as the tim- ing reference for transfer of information on the n0mdio signal. n0mdc is an aperiodic signal that has no maximum high or low times. the minimum high and low times for n0mdc will be 160 ns each, and the minimum period for n0mdc will be 400 ns. 0unlv n0mdio io n0mdio is the bidirectional data signal between the mac and the phy that is clocked by n0mdc. hiz un lv ethernet controller 1 n1txclk i continuous clock input for synchronization of transmit data. 25 mhz when operating at 100 mb/s and 2.5 mhz when operating at 10 mb/s. in in lv n1txen o indicates that the data nibble on n1txd[3:0] is valid. muxed with gpio[24]. n1txen is the default signal coming out of hardware reset, runtime reset, and sleep. 0unlv n1txd[3:0] o nibble wide data bus synchronous to n1txclk. for each n1txclk period in which n1txen is asserted, txd[3:0] will have the data to be accepted by the phy. while n1txen is de-asserted the data pre- sented on txd[3:0] should be ignored. muxed with gpio[28:25]. n1 txd[3:0] are the default signals coming out of hardware reset, runtime reset, and sleep. 0unlv n1rxclk i continuous clock that provides the timing reference for the data transfer from the phy to the mac. n1rxclk is sourced by the phy. the n1rxclk shall have a frequency equal to 25% of the data rate of the received signal data stream (typically 25 mhz at 100 mb/s and 2.5 mhz at 10 mb/s) in in lv n1rxdv i indicates that a receive frame is in process and that the data on n1rxd[3:0] is valid. in in lv n1rxd[3:0] i rxd[3:0] is a nibble wide data bus driven by the phy to the mac synchronous with n1rxclk. for each n1rxclk period in which n1rxdv is asserted, rxd[3:0] will transfer four bits of recovered data from the phy to the mac. while n1rxdv is de-asserted, rxd[3:0] will have no effect on the mac. in in lv table 10-3. signal descriptions (continued) signal type description reset during sleep hardware run time
226 amd alchemy? au1000? processor data book - preliminary signal descriptions 30360d n1crs i n1crs is asserted by the phy when either transmit or receive medium is non idle. n1crs is de-asserted by the phy when both the transmit and receive medium are idle. n1crs is an asynchronous input. in in lv n1col i n1col is asserted by the phy upon detection of a collision on the medium, and remains asserted while the collision condition persists. n1col is an asyn- chronous input. the n1col signal is ignored by the mac when operating in the full duplex mode. in in lv n1mdc o n1mdc is sourced by the mac to the phy as the tim- ing reference for transfer of information on the n1mdio signal. n1mdc is an aperiodic signal that has no maximum high or low times. the minimum high and low times for n1mdc will be 160 ns each, and the minimum period for n1mdc will be 400 ns. 0unlv n1mdio io n1mdio is the bidirectional data signal between the mac and the phy that is clocked by n1mdc. 0unlv i 2 s i2sclk o serial bit clock. muxed with gpio[30]. i2sclk is the default signal coming out of hardware reset, runtime reset, and sleep. 0unlv i2sword o word clock typically configured to the sampling fre- quency (fs). muxed with gpio[31]. i2sword is the default signal coming out of hardware reset, runtime reset, and sleep. 0unlv i2sdi i serial data input sampled on the rising edge of i2sclk. note that i2sdi is used as the input for bidi- rectional operation only, in which case it is used in conjunction with i2sdio as the output ( i2s_config [pd]=0). muxed with gpio[8]. gpio[8] is the default signal coming out of hardware reset, runtime reset, and sleep. system note : for systems that use the i 2 s interface for unidirectional operation (i2sdi not used), the gpio[8] function is available but with the following restrictions: when i2sdio is configured as an input , gpio[8] can be used only as an output. when i2sdio is configured as an output , the i 2 s receive function must be disabled if gpio[8] is to be used as an input. na na lv table 10-3. signal descriptions (continued) signal type description reset during sleep hardware run time
amd alchemy? au1000? processor data book - preliminary 227 signal descriptions 30360d i2sdio io configurable as input or output. as input data should be presented on rising edge. as output, data will be valid on rising edge. muxed with gpio[29]. i2sdio is the default signal coming out of hardware reset, runtime reset, and sleep. 0unlv ac-link acsync o fixed rate sample sync. muxed with s1dout. acsync is the default signal coming out of hardware reset, runtime reset, and sleep. 00lv acbclk i serial data clock . muxed with s1din. acbclk is the default signal coming out of hardware reset, runtime reset, and sleep. in in lv acdo o tdm output stream. muxed with s1clk. acdo is the default signal coming out of hardware reset, runtime reset, and sleep. 00lv acdi i tdm input stream. in in lv acrst# o codec reset. muxed with s1den. acrst# is the default signal coming out of hardware reset, runtime reset, and sleep. 10lv ejtag trst# i asynchronous tap reset. in in lv tdi i test data input to the instruction or selected data reg- isters. sampled on the rising edge of tck. in in lv tdo o test data output from the in struction or data register. transitions occur on the falling edge (valid on rising edge) of tck. hiz un lv tms i control signal for tap controller. sampled on the ris- ing edge of tck. in in lv tck i control clock for updating tap controller and shifting data through instruction or selected data register. in in lv test tc[3:0] i test clock inputs (not used in typical application). should be pulled low for normal operation. in in lv testen i test enable (not used in typical applications). should be pulled low for normal operation. in in lv gpio gpio[1:0] ioz general purpose io. hiz dep (note 1) lv gpio[3:2] ioz general purpose io. muxed with extclk[1:0]. gpio[3:2] are the default signals coming out of hard- ware reset, runtime reset, and sleep. hiz dep (note 1) lv gpio[4] ioz general purpose io. can be configured as dma_req0. hiz dep (note 1) lv table 10-3. signal descriptions (continued) signal type description reset during sleep hardware run time
228 amd alchemy? au1000? processor data book - preliminary signal descriptions 30360d gpio[5] ioz general purpose io. can be configured as dma_req1. hiz dep (note 1) lv gpio[6] ioz general purpose io. muxed with smromcke. if romsel and romsize are configured to boot from synchronous mask rom, the smromcke signal is selected for the pin coming out of reset; otherwise, gpio[6] is selected. hiz dep (note 1) lv gpio[7] ioz general purpose io. hiz dep (note 1) lv gpio[8] ioz general purpose io. muxed with i2sdi. gpio[8] is the default signal coming out of hardware reset, runtime reset, and sleep. system note : for systems that use the i 2 s interface for unidirectional operation (i2sdi not used), the gpio[8] function is available but with the following restrictions: when i2sdio is configured as an input , gpio[8] can be used only as an output. when i2sdio is configured as an output , the i 2 s receive function must be disabled if gpio[8] is to be used as an input. hiz dep (note 1) lv gpio[9] ioz general purpose io. muxed with u3cts. gpio[9] is the default signal coming out of hardware reset, runt- ime reset, and sleep. system note : for systems that use the uart3 inter- face without the optional modem control signals ( sys_pinfunc [ur3]=0), the modem status interrupts must be disabled ( uart3_inten [mie]=0) to avoid false uart3 interrupts when us ing gpio[9], gpio[10], gpio[11], or gpio[12] as an input. hiz dep (note 1) lv gpio[10] ioz general purpose io. muxed with u3dsr. gpio[10] is the default signal coming out of hardware reset, runt- ime reset, and sleep. system note : for systems that use the uart3 inter- face without the optional modem control signals ( sys_pinfunc [ur3]=0), the modem status interrupts must be disabled ( uart3_inten [mie]=0) to avoid false uart3 interrupts when us ing gpio[9], gpio[10], gpio[11], or gpio[12] as an input. hiz dep (note 1) lv gpio[11] ioz general purpose io. muxed with u3dcd. gpio[11] is the default signal coming out of hardware reset, runt- ime reset, and sleep. system note : for systems that use the uart3 inter- face without the optional modem control signals ( sys_pinfunc [ur3]=0), the modem status interrupts must be disabled ( uart3_inten [mie]=0) to avoid false uart3 interrupts when us ing gpio[9], gpio[10], gpio[11], or gpio[12] as an input. hiz dep (note 1) lv table 10-3. signal descriptions (continued) signal type description reset during sleep hardware run time
amd alchemy? au1000? processor data book - preliminary 229 signal descriptions 30360d gpio[12] ioz general purpose io. muxed with u3ri. gpio[12] is the default signal coming out of hardware reset, runt- ime reset, and sleep. system note : for systems that use the uart3 inter- face without the optional modem control signals ( sys_pinfunc [ur3]=0), the modem status interrupts must be disabled ( uart3_inten [mie]=0) to avoid false uart3 interrupts when us ing gpio[9], gpio[10], gpio[11], or gpio[12] as an input. hiz dep (note 1) lv gpio[13] ioz general purpose io. muxed with u3rts. gpio[13] is the default signal coming out of hardware reset, runt- ime reset, and sleep. hiz dep (note 1) lv gpio[14] ioz general purpose io. mu xed with u3dtr. gpio[14] is the default signal coming out of hardware reset, runt- ime reset, and sleep. hiz dep (note 1) lv gpio[15] ioz general purpose io. muxed with irfirsel. gpio[15] is the default signal coming out of hardware reset, runtime reset, and sleep. hiz dep (note 1) lv gpio[16] ioz general purpose io. muxed with s0dout. s0dout is the default signal coming out of hardware reset, runtime reset, and sleep. na na lv gpio[17] ioz general purpose io. muxed with s0clk. s0clk is the default signal coming out of hardware reset, runt- ime reset, and sleep. na na lv gpio[18] ioz general purpose io. muxed with s0den. s0den is the default signal coming out of hardware reset, runt- ime reset, and sleep. na na lv gpio[19] ioz general purpose io. muxed with irdatx. irdatx is the default signal coming out of hardware reset, runt- ime reset, and sleep. na na lv gpio[20] ioz general purpose io. muxed with u0txd. u0txd is the default signal coming out of hardware reset, runt- ime reset, and sleep. na na lv gpio[21] ioz general purpose io. muxed with u1txd. u1txd is the default signal coming out of hardware reset, runt- ime reset, and sleep. na na lv gpio[22] ioz general purpose io. muxed with u2txd. u2txd is the default signal coming out of hardware reset, runt- ime reset, and sleep. na na lv gpio[23] ioz general purpose io. muxed with u3txd. u3txd is the default signal coming out of hardware reset, runt- ime reset, and sleep. na na lv gpio[24] ioz general purpose io. muxed with n1txen. n1txen is the default signal coming out of hardware reset, runtime reset, and sleep. na na lv gpio[28:25] ioz general purpose io. muxed with n1txd[3:0]. n1txd[3:0] are the default signals coming out of hardware reset, runtime reset, and sleep. na na lv table 10-3. signal descriptions (continued) signal type description reset during sleep hardware run time
230 amd alchemy? au1000? processor data book - preliminary signal descriptions 30360d gpio[29] ioz general purpose io. muxed with i2sdio. i2sdio is the default signal coming out of hardware reset, runt- ime reset, and sleep. na na lv gpio[30] ioz general purpose io. muxed with i2sclk. i2sclk is the default signal coming out of hardware reset, runt- ime reset, and sleep. na na lv gpio[31] ioz general purpose io. muxed with i2sword. i2sword is the default signal coming out of hard- ware reset, runtime reset, and sleep. na na lv external clocks extclk[1:0] o general-purpose extern al clocks. one of these clock outputs can be used as an oversampled audio clock (audclk or mclk) output with i 2 s port as it is syn- chronous to i2sclk and i2sword. typically it should be programmed to 128*fs, 256*fs, 384*fs or 512*fs for this application. muxed with gpio[3:2]. gpio[3:2] are the default sig- nals coming out of hardware reset, runtime reset, and sleep. na na lv system dma requests dma_req0 (gpio[4]) i gpio[4] can be configur ed as an external, system dma request input. hiz hiz lv dma_req1 (gpio[5]) i gpio[5] can be configur ed as an external, system dma request input. hiz hiz lv system clocks and reset xti12 i internally compensated 12 mhz (typical) crystal input. termination note: the termination depends on the application as follows: crystal?connect crystal between xti12 and xto12. overdriven?connect to external 12 mhz clock source and drive complementary to xto12. xto12 o internally compensated 12 mhz (typical) crystal out- put. termination note: the termination depends on the application as follows: crystal?connect crystal between xti12 and xto12. overdriven?connect to external 12-mhz clock source and drive complementary to xti12. table 10-3. signal descriptions (continued) signal type description reset during sleep hardware run time
amd alchemy? au1000? processor data book - preliminary 231 signal descriptions 30360d xti32 i internally compensated 32.768-khz (typical) crystal input. termination note: the termination depends on the application as follows: crystal?connect crystal between xti32 and xto32. overdriven?connect to external 32.768-khz clock source through a series 10-k ? resistor and drive com- plementary to xto32. not used?connect to v ddx . xto32 o internally compensated 32.768 khz (typical) crystal output. termination note: the termination depends on the application as follows: crystal?connect crystal between xti32 and xto32. overdriven?connect to external 32.768 khz clock source through a series 10 kohm resistor and drive complementary to xti32. not used?connect to v ddx . resetin# i cpu reset input. in in lv resetout# o buffered output of cp u reset input (resetin#). 0 0 0 romsel i determines if boot is from rom or smrom. romsel should be terminated appropriately as these signals should not change during runtime. in in lv romsize i latched at the rising edge of reset to determine if rom width is 16 or 32 bits. romsize should be terminated appropriately as these signals should not change during runtime. in in lv power management pwr_en o power enable output. this signal is intended to be used as the regulator enable for v ddi (core power). 110 vddxok i input to signal that v ddx is stable. in in lv power/ground v ddi p internal core voltage. follow the power supply layout guidelines in section 11.9.2 "decoupling recommen- dations" on page 254. v ddx p external i/o voltage. follow the power supply layout guidelines in section 11.9.2 "decoupling recommen- dations" on page 254. v ss g ground. xpwr12 p 12 mhz (typical) oscillator and pll power. connect to v ddx through a 10 ohm resistor. in addition a 22 f capacitor in parallel with a 0.01 f capacitor should be placed from this pin to xagnd12. xagnd12 g 12 mhz (typical) oscillator and pll ground. table 10-3. signal descriptions (continued) signal type description reset during sleep hardware run time
232 amd alchemy? au1000? processor data book - preliminary signal descriptions 30360d xpwr32 p 32.768 khz (typical) oscillator and pll power. because xpwr32 powers other circuitry also, it should be connected even if the oscillator is not used. connect to v ddx through a 10 ohm resistor. in addi- tion a 22 f capacitor in parallel with a 0.01 f capac- itor should be placed from this pin to xagnd32. xagnd32 g 32.768khz (typical) oscillator and pll ground. note 1. depends on sys_trioutrd and sys_outputset . during a runtime reset, sys_pinfunc returns to its default value, but the gpio control registers sys_trioutrd and sys_outputset remain unchanged. table 10-3. signal descriptions (continued) signal type description reset during sleep hardware run time
amd alchemy? au1000? processor data book - preliminary 233 signal descriptions 30360d
amd alchemy? au1000? processor data book - preliminary 234 11 electrical and thermal specifications 30360d 11.0 electrical and thermal specifications this chapter provides preliminary electrical specifications for the au1000 processor, including the following: absolute maximum ratings thermal characteristics dc parameters ac parameters power-up, reset, sleep, and idle timing external clock specifications crystal specifications system design considerations 11.1 absolute maximum ratings table 11-1 shows the absolute maximum ratings for the au1000 processor. these ratings are stress ratings, operating at or beyond these ratings for extended periods of time may result in damage to the au1000 processor. unless otherwise designated all voltages are relative to v ss . table 11-1. absolute maximum ratings parameter description min max unit v ddi core voltage v ss - 0.5 2 v v ddx i/o voltage v ss - 0.5 3.6 v xpwr12, xpwr32 oscillator voltage v ss - 0.5 3.6 v v in voltage applied to any pin v ss - 0.5 v ddx + 0.5 v t case for: au1000-266mcc, AU1000-400MCC, au1000-500mcc package operating temperature 0 85 c t case for: au1000-266mci package operating temperature -40 100 c t s storage temperature -40 125 c
amd alchemy? au1000? processor data book - preliminary 235 electrical and thermal specifications 30360d 11.1.1 undershoot the minimum dc voltage on input or i/o pins is -0.5v. however, during voltage transitions, the device can tolerate under- shoot to -2.0v for up to 20 ns, as shown in figure 11-1. figure 11-1. voltage undershoot tolerances for input and i/o pins 11.1.2 overshoot the maximum dc voltage on input or i/o pins is (v ddx + 0.5) v. however, during voltage transitions, the device can toler- ate overshooting v ddx to (v ddx + 2.0) v for up to 20 ns, as shown in figure 11-2. figure 11-2. voltage overshoot tolerances for input and i/o pins 11.2 thermal characteristics table 11-2 shows the thermal characteristics for the au1000 processor. table 11-2. thermal characteristics parameter description value unit ja thermal resistance from device junction to ambient. 28.0 (note 1) note 1. measured without forced air?natural convection only. c/w y jt thermal characterization parameter measured from device junction to top center of package. (see jesd51-2, sec. 4.) 4.4 c/w 20 ns ?2.0v ?0.5v v il allowed voltages 20 ns 20 ns v ddx,y + 2.0v v ddx,y + 0.5v v ddx,y allowed voltages 20 ns 20 ns 20 ns
236 amd alchemy? au1000? processor data book - preliminary electrical and thermal specifications 30360d 11.3 dc parameters table 11-3 shows the dc parameters for the au1000 processor. unless otherwise designated all voltages are relative to v ss . the operating requirements for the power supply voltages (v ddx and v ddi ) are given in the sections describing the dc characteristics for the different operating frequencies, beginnin g with section 11.3.1 "power and voltage for 266, 400, and 500 mhz rated parts" on page 236. 11.3.1 power and voltage for 266, 400, and 500 mhz rated parts the tables that follow give the voltage and power parameters for the individual mhz rated parts. table 11-3. dc parameters symbol parameter min nominal max unit v ihx input high voltage 2.4 v v ilx input low voltage 0.2 * v ddx v v ohx @ 2 ma output high voltage 0.8 * v ddx v v olx @ 2 ma output low voltage 0.2 * v ddx v l i input leakage current 5 a c in input capacitance (note 1) note 1. this parameter is by design and not tested. 5pf i xpwr12 (note 2) note 2. does not apply during sleep. xpwr12 current 1 3 ma i xpwr32 (note 2) xpwr32 current 1 3 ma table 11-4. voltage and power parameters for 266 mhz part parameter min typ max unit v ddi 1.4 1.5 1.6 v v ddx , xpwr12, xpwr32 (note 1) note 1. xpwr12 and xpwr32 should be connected to v ddx . for a description of this circuit connection, see the entries for xpwr12 and xpwr32 in table 10-3 "signal descriptions" on page 219. 3.0 3.3 3.6 v power: v ddi 195 525 (note 2) note 2. while the maximum power numbers should be used w hen specifying a r egulator for a system, the numbers are well above the typical power consumption because none of the po wer-saving design features (such as idle, or the au- tomatic system bus divider) are enabled. no te that because the part icular application softwa re and external loading affect the power consumption on a give n system design, certain conditions may exist which could cause the max- imum power consumption to be different than shown. mw power: v ddx 105 325 (note 2) mw idle power (note 3) note 3. idle power is the power measured when the processor core is in the idle0 state. (idle0 maintains cache coher- ency by snooping the system bus; idle 1 does not snoop t he bus. because caches are turned off during the idle1 state, idle1 consumes less power th an idle0.) typically the idle state is entered during an operating system?s wait loop in which the core has no processes to run. while the processor core is in idle, clocks to the core are gated off; however, all registers retain their values, and the pe ripherals, dma engine, and the interrupts remain active so that the system is still functional. 210 mw sleep current (v ddi = v ss )50ua
amd alchemy? au1000? processor data book - preliminary 237 electrical and thermal specifications 30360d table 11-5. voltage and power parameters for 400 mhz part parameter min typ max unit v ddi 1.4 1.5 1.6 v v ddx , xpwr12, xpwr32 (note 1) note 1. xpwr12 and xpwr32 should be connected to v ddx . for a description of this circuit connection, see the entries for xpwr12 and xpwr32 in table 10-3 "signal descriptions" on page 219. 3.0 3.3 3.6 v power: v ddi 365 725 (note 2) note 2. while the maximum power numbers should be used w hen specifying a r egulator for a system, the numbers are well above the typical power consumption because none of the po wer-saving design features (such as idle, or the au- tomatic system bus divider) are enabled. no te that because the part icular application softwa re and external loading affect the power consumption on a give n system design, certain conditions may exist which could cause the max- imum power consumption to be different than shown. mw power: v ddx 135 465 (note 2) mw idle power (note 3) note 3. idle power is the power measured when the processor core is in the idle0 state. (idle0 maintains cache coher- ency by snooping the system bus; idle 1 does not snoop t he bus. because caches are turned off during the idle1 state, idle1 consumes less power th an idle0.) typically the idle state is entered during an operating system?s wait loop in which the core has no processes to run. while the processor core is in idle, clocks to the core are gated off; however, all registers retain their values, and the pe ripherals, dma engine, and the interrupts remain active so that the system is still functional. 222 mw sleep current (v ddi = v ss )50a table 11-6. voltage and power parameters for 500 mhz part parameter min typ max unit v ddi 1.71 1.8 1.89 v v ddx , xpwr12, xpwr32 (note 1) note 1. xpwr12 and xpwr32 should be connected to v ddx . for a description of this circuit connection, see the entries for xpwr12 and xpwr32 in table 10-3 "signal descriptions" on page 219. 3.0 3.3 3.6 v power: v ddi 750 1300 (note 2) note 2. while the maximum power numbers should be used w hen specifying a r egulator for a system, the numbers are well above the typical power consumption because none of the po wer-saving design features (such as idle, or the au- tomatic system bus divider) are enabled. no te that because the part icular application softwa re and external loading affect the power consumption on a give n system design, certain conditions may exist which could cause the max- imum power consumption to be different than shown. mw power: v ddx 150 575 (note 2) mw idle power (note 3) note 3. idle power is the power measured when the processor core is in the idle0 state. (idle0 maintains cache coher- ency by snooping the system bus; idle 1 does not snoop t he bus. because caches are turned off during the idle1 state, idle1 consumes less power th an idle0.) typically the idle state is entered during an operating system?s wait loop in which the core has no processes to run. while the processor core is in idle, clocks to the core are gated off; however, all registers retain their values, and the pe ripherals, dma engine, and the interrupts remain active so that the system is still functional. 347 mw sleep current (v ddi = v ss )50a
238 amd alchemy? au1000? processor data book - preliminary electrical and thermal specifications 30360d 11.4 ac parameters this section describes the ac parameters for i/o devices in the au1000 processor. each class of output signal has differ- ent capacitive loads. as the ca pacitance on the load increases the propagati on delay will increase. these specifications assume the maximum capacitive load to be 50 pf for all i/o signals other than the sdram interface. the timing of those signals which have synchronous relationshi ps or have a defined requirement are given. the timing dia- grams are shown to illustrate the timing only and should not necessarily be interpreted as the functional timing of the port. it is assumed that the timing and/or functi onality of the protocol rela ted to the port is adhered to by the external system. th e protocol timing is not necessarily present ed here and the appropriate section or s pecification should be referenced for com- plete functional timing parameters. timing measurements are made from 50% threshold to 50% threshold. certain timing parameters are based of f of the internal system bus clock. when this is th e case the symbol t sys is used. t sys is defined in nanoseconds as: t sys = sd/cpu the symbol cpu should be interpreted as the cpu clock speed in mhz as set by the cpu pll. see section 7.1 "clocks" on page 168 for details. the symbol sd is the system bus di vider. see section 7.4 "power management" on page 188 for details.
amd alchemy? au1000? processor data book - preliminary 239 electrical and thermal specifications 30360d 11.4.1 sdram timing and loading the sdram controller loading limits are as follows: sdram outputs excluding the clocks and chip-selects can support a maximum capacitive load of 35 pf (six 5 pf gate loads and 5 pf representing the trace). each clock and each chip-select supports a maximum capacitive load of 15 pf (two 5 pf gate loads and 5 pf repre- senting the trace). the sdram is a high speed interface. reflection and propagat ion delays should be accounted for in the system design. as a general rule of thumb, unterminated etc hes should be kept to 6 inches or less. figure 11-3. sdram timing table 11-7. sdram cont roller interface signal symbol parameter min max unit sdclk[n] tsdclk sdclk[n] clock cycle ns sdcs[n#], sdras#, sdcas#, sdwe#, sdba[1:0], sda[12:0], sdqm[3:0]#, sdd[31:0] (output) tsdd delay from sdclk[n] ns sdd[31:0] (input) tsdsu data setup to sdclk[n] 3 ns sdd[31:0] (input) tsdh data hold from sdclk[n] 2 ns 2 t sys t sdclk 4 -------------- 1.5 ? t sdclk 4 -------------- 2 + tsdh tsdsu tsdd tsdclk sdclk sdcs[n]#, sdras#, sdcas#, sdwe#, sdba[1:0], sda[12:0], sdqm[3:0]#, sdd[31:0] (output) sdd[31:0] (input)
240 amd alchemy? au1000? processor data book - preliminary electrical and thermal specifications 30360d 11.4.2 static bus controller timing the timing presented in registers mem_sttime n are not presented here. the paramete rs in these registers are presented in a certain number of clock cycles and are accurate to within 2 ns. figure 11-4. static ram, i/ o device and flash timing table 11-8. static ram, i/o device and flash timing signal symbol parameter min max unit rben[3:0]#, roe#, rad[31:0], burstsize[2:0] trcd delay from rcsn#. -2 +2 ns rd[31:0] (read) trsu data setup to rcs n # trsu does not apply when ewait# is used to extend the cycle. 15 ns rd[31:0] (read) trsue data setup to ewait#. note that trsue applies only when ewait# is used to extend the cycle. 0ns rd[31:0] (read) trh data hold from rcsn#. 0 ns rd[31:0] (write) trod delay from rwe# to data out. -2 2 ns ewait# trwsu ewait# setup to rcsn# for reads, or rwe# for writes. if ewait# does not meet this setup time the cycle will not be held. 3 * t sys + 15 ns rcs# (reads), rwe# (writes) trwd delay from ewait#. 2 * t sys 3 * t sys + 15 burstsize[2:0] trbd delay from rcsn#. t sys + 2 rben[3:0]#, roe#, rad[31:0] tr c d tr c d tr s u tr h tr w s u tr w d rcsn# tr w s u tr w d rwe# ewait# rd[31:0] (input) burstsize[2:0] rd[31:0] (output) tr c d tr b d tr o d trsue
amd alchemy? au1000? processor data book - preliminary 241 electrical and thermal specifications 30360d figure 11-5. pcmcia host adapter timing table 11-9. pcmcia timing signal symbol parameter min max unit preg#, rad[31:0], rd[31:0] (output) tpcd delay from pce[n]#. -2 +2 ns pios16# tpios pios16# setup to pior#, piow#. 4 * tsys + 15 ns pios16# tpioh pios16# hold from pior#, piow#. 0ns roe# tpoed roe# delay from poe#, pior#. -2 +2 ns rd[15:0] (input) tpsu data se tup to poe#, pior#. note that tpsu does not apply when pwait# is used to extend the cycle. tsys + 15 ns rd[15:0] (input) tpsup data se tup to pwait#. note that tpsup applies only when pwait# is used to extend the cycle. 0ns rd[31:0] tph data hold from poe#, pior#. 0 ns pwait# tpwsu pwait# setup to poe#, pwe#, pior#, piow#. if pwait# does not meet this setup time the cycle will not be held. 4 * tsys + 15 ns poe#, pwe#, pior#, piow# tpwd poe#, pwe#, pior#, piow# delay from pwait#. 3 * tsys 4 * tsys + 15 ns preg#, rad[31:0], rd[15:0] (output) tpcd tpcd pwe#, piow# poe#, pior# pios16# pwait# roe# tpcd tph tpsu tpwsu tpwd tpios tpioh tpoed pce[n]# rd[15:0] (input) tpsup
242 amd alchemy? au1000? processor data book - preliminary electrical and thermal specifications 30360d figure 11-6. lcd interface timing 11.4.3 gpio input timing requirements 11.4.3.1 gpio input edge rate for level-sensitive gpio inputs, edge rates as slow as 5 ms can be used. note that no hyster esis is used on the inputs so for edge-sensitive inputs (such as clocks and edge-triggered interrupts) use a 20-ns (or faster) edge rate to ensure that noise does not cause false edges as the sign al transitions through the threshold region. table 11-10. lcd timing signal symbol parameter min max unit lclk tlclk lclk period. this parameter is programmed in mem_stcfg0 [d5]. tsys * 4 tsys * 5 ns rcsn#, rad[31:0], rd[15:0] (output) tlcd delay from lclk. -2 2 ns rd[15:0] (input) tlsu data se tup to lrd[n]#. tsys + 15 ns rd[15:0] (input) tlh data hold from lrd[n]#. 0 ns lwait# tlwsu lwait# setup to lrd[n] for reads, or lwr[n]# for writes. if lwait# does not meet this setup time the cycle will not be held. 4 * tsys + tlclk + 15 ns lrd[n]# (reads), lwr[n]# (writes) tlwd delay from lwait#. 4 * tsys + tlclk + 15 ns rcsn# rad[31:0], rd[15:0] (output) tlcd tlcd tlh tlsu lwr[n]# lrd[n]# lwait# rd[15:0] (input) tlwsu tlwd tlclk lclk
amd alchemy? au1000? processor data book - preliminary 243 electrical and thermal specifications 30360d 11.4.3.2 gpio interrupt timing for system designs using gpio signals as level-triggered interrupts, the signal level must be st able for at least 10 ns in order for a signal state change to be detected. see table 11-11 and figure 11-7. figure 11-7. gpio interrupt timing 11.4.4 peripheral timing this section contains the electrical timing s pecifications for the integrated peripherals. table 11-11. gpio timing for interrupts signal symbol parameter min max unit gpio[n] tmin minimum high or low time for interrupt. the level is programmable. this timing reflects the minimum active period for the level programmed. 10 ns tmin gpio[n]
244 amd alchemy? au1000? processor data book - preliminary electrical and thermal specifications 30360d 11.4.4.1 ethernet mii timing figure 11-8. ethernet mii timing diagram table 11-12. ethernet mii timing signal symbol parameter min max unit n0txclk, n0rxclk, n1txclk, n1rxclk teth ethernet transmit/receive clock cycle time (25% of data rate) 40 100 ppm (100 mbps) 400 100 ppm (10 mbps) ns ethernet transmit/ receive clock duty cycle 35 65 % n0txen, n0txd[3:0], n1txen, n1txd[3:0] ted delay from txclk to txen, txd[3:0] 0 25 ns n0rxd[3:0], n0rxdv, n1rxd[3:0], n1rxdv tesu setup time before rxcclk for rxd, and rxdv 10 ns teh hold time from rxclk for rxd, and rxdv 10 ns n0mdc, n1mdc tmdc mdc cycle time system bus clock / 160 mdc duty cycle 40 60 % n0mdio, n1mdio tmdd delay from mdc to mdio 0 300 ns tmsu setup time before mdc for mdio 10 ns tmh hold time from mdc for mdio 10 ns tmz delay from mdc to mdio tri-state 0 300 ns n0crs, n0col, n1crs, n1col ta minimum active time ted teth n n txd[3:0], n n txen n n txclk teth teh tesu n n rxclk n n rxd[3:0], n n rxdv tmz tmdd tmh tmsu tmdc n n mdc n n mdio ta n n crs, n n col
amd alchemy? au1000? processor data book - preliminary 245 electrical and thermal specifications 30360d 11.4.4.2 i 2 s timing note: i2sdi and i2sdio (as an input) are shown to have a 0 ns hold time relative to the falling edge. this design allows for the data source to transition data from the falling edge to the next data value. i2sdio input and output timing is shown on the same signal. in practice, the signal direction can be programmed as only one or the other. figure 11-9. i 2 s timing diagram table 11-13. i 2 s interface timing signal symbol parameter min max unit i2sclk ti2s i 2 s interface clock cycle time 40 ns i 2 s clock duty cycle 40 60 % i2sdi, i2sdio, i2sword tid delay from i2sclk to i2sdio and i2sword on output (i2sdio programmed as output) 010ns tisu setup before i2sclk on input (i2sdio programmed as input) 20 ns tih hold after i2sclk on input (i2sdio programmed as input) 0ns tid tid ti2s tih tisu i2sclk i2sword i2sdio i2sdi
246 amd alchemy? au1000? processor data book - preliminary electrical and thermal specifications 30360d 11.4.4.3 ac97 timing note: acrst# is an asynchronous signal controlled by software through the register ac97_config . it has no relation- ship to the other ac97 signals. figure 11-10. ac-link timing diagram table 11-14. ac-link interface timing signal symbol parameter min max unit acbclk tabc ac97 bit clock cycle time 12.288 (typical) mhz tabh ac97 bit clock high time 36 45 ns tabl ac97 bit clock low time 36 45 ns acsync tacs ac97 sync cycle 48 (typical) khz tacsh ac97 sync high time 1.3 (typical) s tacsl ac97 sync low time 19.5 (typical) s acsync acdo acdi tad delay from acbclk to acsync and acdo on output 15 ns tasu setup before acbclk for acdi 10 ns tah hold after acbclk for acdi 10 ns tad tad tacsl tacs tacsh tabh tabc tabl tah tasu acbclk acsync acdo acdi acsync
amd alchemy? au1000? processor data book - preliminary 247 electrical and thermal specifications 30360d 11.4.4.4 ssi timing note: the timing diagrams shown are for rising edge active s n clk and active low s n den. both parameters are pro- grammable. timing will apply to the relative active or inactive edge as stated in the timing table. the timing diagram is to represent timing only, it is not intended to represent the functionality of the port. timing parameters for both ssi ports are identical. only one set of timing is presented with the n representing either 0 or 1. figure 11-11. ssi timing diagram table 11-15. synchronous serial interface timing signal symbol parameter min max unit snclk tclk clock period. this period is programmable. see section 6.8 "ssi interfaces" on page 160 for more information. 200 ns snclk tscd snden to clock delay tclk + 10 ns snden tsed snclk to snden delay tclk + 10 ns sndin tssu sndin setup to active edge of snclk 30 ns sndin tsh sndin hold from active edge of snclk 10 ns sndout tsd sndout delay from inactive edge of snclk 20 ns tclk tssu tsh tsd snden snclk sndout sndin tscd tsed
248 amd alchemy? au1000? processor data book - preliminary electrical and thermal specifications 30360d 11.4.4.5 ejtag interface timing figure 11-12. ejtag timing diagram table 11-16. ejtag interface timing signal symbol parameter min max unit tck tec ejtag tck cycle time 40 ns tech tck high time 10 ns tecl tck low time 10 ns tms, tdi tesu setup before tck for tms and tdi 5 ns teh hold after tck for tms and tdi 3 ns tdo teco delay from tck to tdo on output 15 ns tecz delay from tck to tdo tri-state 15 ns trst# trstl trst# low time 25 ns tecz teco trstl tecl tech tec teh tesu tck tms, tdi tdo trst#
amd alchemy? au1000? processor data book - preliminary 249 electrical and thermal specifications 30360d 11.5 power-up and reset timing this section provides the timing specif ications for the power-up sequence, and the hardware and runtime reset sequences. (see section 8, "power-up, reset and boot" for functional descriptions of the sequences.) 11.5.1 power-up sequence timing figure 11-13. power-up sequence table 11-17. power-up timing parameters parameter description min max unit tvo v ddx at 90% of nominal to vddxok asserted 0 ns tpen vddxok asserted to pwr_en driven high 30 ns tvi pwr_en to v ddi stable 20 ms tvi tpen tvo v ddx vddxok pwr_en v ddi
250 amd alchemy? au1000? processor data book - preliminary electrical and thermal specifications 30360d 11.5.2 hardware reset timing figure 11-14. hardware reset sequence table 11-18. hardware reset timing parameters parameter description min typ max tvxr vddxok asserted to r esetin# de-asserted 0 ns system dependent tvl vddxok low time 1 s trstl resetin# low time 1 s tvro resetin# to resetout# delay max = max[750 ns, 170 ms - tvxr] 600 ns see description trocs resetout# to rcs0#/sdcs0# asserted. 135 ns 1 s tvro tvxr vddxok resetin# resetout# tvl trstl trocs rcs0#/sdcs0#
amd alchemy? au1000? processor data book - preliminary 251 electrical and thermal specifications 30360d 11.5.3 runtime reset timing figure 11-15. runtime reset sequence table 11-19. runtime reset timing parameters parameter description min typ max trstl resetin# low time 1 s trof resetin# falling to resetout# falling max: 25 ns + (0.5 * (cpu clock/2)) see description tror resetin# rising to resetout# rising max: 25 ns + (0.5 * (cpu clock/2)) + (120 * cpu clock) 120 cpu clocks see description trocs resetout# to rcs0#/sdcs 0# asserted. note that the timing values shown assume a 400 mhz cpu clock. 65 ns 500 ns trof trstl v ddx (at nominal voltage) vddxok (asserted high) p wr_en (remains asserted) v ddi (at nominal voltage) resetin# resetout# tror tr o c s rcs0#/sdcs0#
252 amd alchemy? au1000? processor data book - preliminary electrical and thermal specifications 30360d 11.6 asynchronous signals gpio - the gpio signals are driven by software. note, however, when gpio signals are used as inputs, there are timing requirements to ensure signal state changes are recognized cl eanly; see section 11.4.3, "gpio input timing require- ments". uart - all uart signals are asynchronous to other external signals. usb- all usb signals are asynchronous to other external si gnals. the usb protocol should be followed for appropriate operation. 11.7 external clock specifications the extclk[1:0] external clocks have a maximum frequency rating of (f max / 16), where f max is the maximum frequency rating for the part. table 11-20 provides the extclk[1:0] specifications. table 11-20. external clock extclk[1:0] specifications characteristic 266 mhz 400 mhz 500 mhz unit min max min max min max frequency 16.63 25 31.25 mhz frequency jitter 4 4 4 % duty cycle 40 60 40 60 40 60 %
amd alchemy? au1000? processor data book - preliminary 253 electrical and thermal specifications 30360d 11.8 crystal specifications note that load capacitors for the external oscillators are inte grated into the au1000 processor so no external circuitry is required when using the specified crystal. for design layout considerations concerning the crystals, see section 11.9.1, crystal layout. table 11-21 provides the specification for the parallel resonan t 12 mhz crystal to be placed between xti12 and xto12 and table 11-22 provides the specification for the parallel res onant 32 khz crystal to be placed between xti32 and xto32. table 11-21. 12 mhz crystal specification specification min typ max unit resonant frequency 11 12 15 mhz frequency stability 100 ppm motional resistance 60 ohms shunt capacitance <5 7 pf load capacitance (note 1) note 1. this capacitance is integrated on the au1000. 81220pf drive level 100 w crystal type at cut table 11-22. 32.768 khz crystal specification specification min typ max unit resonant frequency 32.768 khz equivalent series resistance 50k ohms shunt capacitance 1.5 2.0 pf load capacitance (note 1) note 1. this capacitance is integrated on the au1000. 612pf motional capacitance 3 4 ff drive level 1w quality factor 40k crystal type tuning fork
254 amd alchemy? au1000? processor data book - preliminary electrical and thermal specifications 30360d 11.9 system design considerations this section provides informati on for system-level design issues. 11.9.1 crystal layout the crystal layouts are critical. without using vias, place trac es directly over a ground plane on the top layer with keep-outs on all surrounding sides. trace lengths should be less than 0.5 inches, and trace widths should be set to the minimum sig- nal trace width for the design. be sure not to allow other sig nals to come within 0.025 inches of these sensitive analog sig- nals. 11.9.2 decoupling recommendations this section provides recommendations for minimizing noise in a system. note that specific decoupling requirements are system dependent. to filter noise on the power supplies, v ddx and v ddi , as well as xpwr12 and xpwr32, should be bypassed to ground using 10 f capacitors: for each of the four sides of the package, place a capacitor within 0.5 inches. to filter high-frequency noise, capacitors in the 10 nf range should be placed under the package: for minimal high-frequency decoupling, use six to eight 10 nf capacitors. for systems requiring a broader spectrum of high-frequency noise be filtered, use four 15 nf and four 6.8 nf capacitors.
amd alchemy? au1000? processor data book - preliminary 255 electrical and thermal specifications 30360d
amd alchemy? au1000? processor data book - preliminary 256 12 packaging, pin assignment and ordering information 30360d 12.0 packaging, pin assignment and ordering information this chapter provides information about the au1000 processor package and pinout, as well as providing ordering informa- tion. the contents of the chapt er are organized as follows: the package dimensions are shown in figure 12-1 "pack age dimensions" on page 257 . the au1000 is packaged in a 324-pin lf-pbga device. table 12-2 "connection diagram ? top view" on page 259 (and continued on page 260) is the connection diagram showing the pin and signal placement on the package. for pins that provide multiple signal functions, the default signal is shown first followed by the alternate signal in parentheses. note that the black square in the upper-left hand corner indicates where the device is keyed. the pin assignment list sorted by pin number is table 12-1 on page 261 the pin assignment list sorted alphapetically by default signal is table 12-2 on page 265. the pin assignment listing for the alternate signals is table 12-3 on page 268 (alphabetically sorted by alternate signal) ordering information is supplied on page 269.
amd alchemy? au1000? processor data book - preliminary 257 packaging, pin assignment and ordering information 30360d 12.1 mechanical package figure 12-1. package dimensions top view side view pin 1 i.d. 23 23 b a detail k notes 1. dimensioning and tolerancing per asme y14.5m-1994 . 2. all dimensions are in millimeters . 3. ball position designation per jesd 95-1, spp-010. 4. ball diameter is measured at its maximum dimension in a plane parallel to datum c. 5. this package meets jedec outline mo-192 rev e, variation daj-1, with the exception of the ball diameter size tolerance and coplanarity.
258 amd alchemy? au1000? processor data book - preliminary packaging, pin assignment and ordering information 30360d figure 12-1. package dimensions (continued) ?0.10 m c ?0.25 m c a b bottom view 22 1.0 a1 corner 1.0 22 324 x ? 0.5 +/-0.1 4 0.5 0.5 0.15 c 0.10 c 0.25 min 1.50 max 0.87 min seating plane detail k c 5 5
amd alchemy? au1000? processor data book - preliminary 259 packaging, pin assignment and ordering information 30360d 12.2 pin assignments . figure 12-2. connection diagram ? top view 1 2 3 4 5 6 7 8 9 10 11 12 a s0dout (gpio[16]) u2rxd s0clk (gpio[17]) i2sdio (gpio[29]) acsync (s1dout) n0rxd1 n0rxd2 u0txd (gpio[20]) u2txd (gpio[22]) n0rxdv n0txen n1txclk b usbh1m usbdm (usbh0m) u1rxd n0txclk acbclk (s1din) n0rxd0 i2sclk (gpio[30]) i2sword (gpio[31]) u1txd (gpio[21]) n0rxclk n0col n0txd1 c gpio[12] (u3ri) tck usbh1p s0den (gpio[18]) irdatx (gpio[19]) n0crs acrst# (s1den) acdo (s1clk) n0rxd3 u3txd (gpio[23]) n0txd0 n0txd2 d tdi gpio[11] (u3dcd) u0rxd usbdp (usbh0p) u3rxd acdi v ddx v ddx v ddx v ddi v ddi v ddi e tdo gpio[9] (u3cts) gpio[10] (u3dsr) irdarx f rcs2# rcs3# gpio[8] (i2sdi) s0din g roe# rcs0# rcs1# v ddx h rben2# rben3# rwe# v ddx j rad31 rben0# rben1# v ddx v ss v ss v ss v ss k rad28 rad29 rad30 v ddi v ss v ss v ss v ss l rad25 rad27 rad26 v ddi v ss v ss v ss v ss m rad23 rad24 rad22 v ddi v ss v ss v ss v ss n rad21 rad20 rad18 v ddx v ss v ss v ss v ss p rad19 rad17 rad15 v ddx v ss v ss v ss v ss r rad16 rad14 rad10 v ddx t rad13 rad12 rad7 v ddx u rad11 rad9 rad4 rad0 v rad8 rad6 rad2 rd23 w rad5 rad3 rd30 rd22 rd19 v ddx v ddx v ddx v ddi lclk v ddi v ddi y rad1 rd31 rd26 rd20 rd16 rd13 rd10 rd7 rd3 lwr1# lrd1# pce1# aa rd29 rd27 rd25 rd18 rd15 rd12 rd9 rd6 rd4 rd0 lwait# lrd0# ab rd28 rd24 rd21 rd17 rd14 rd11 rd8 rd5 rd2 rd1 ewait# lwr0# 1 2 3 4 5 6 7 8 9 10 11 12
260 amd alchemy? au1000? processor data book - preliminary packaging, pin assignment and ordering information 30360d figure 12-2. connection diagram ? top view (continued) 13 14 15 16 17 18 19 20 21 22 n0txd3 n1rxd0 n1rxd1 n0mdio gpio[15] (irfirsel) n1txen (gpio[24]) n1txd3 (gpio[28]) sdd0 sdd3 sdd5 a n1crs n0mdc gpio[14] (u3dtr) n1rxd3 n1txd0 (gpio[25]) n1rxdv n1mdc sdd1 sdd4 sdd6 b gpio[13] (u3rts) n1rxd2 n1rxclk n1txd2 (gpio[27]) n1txd1 (gpio[26]) n1col n1mdio sdd2 sdd10 sdd11 c v ddi v ddx v ddx v ddx sdd9 sdd8 sdd7 sdd12 sdd13 sdd14 d v ddx sdd15 sdd16 sdd17 e v ddx sdd18 sdd19 sdd20 f v ddx sdd21 sdd22 sdd23 g v ddi sdd24 sdd25 sdd26 h v ss v ss v ddi sdd27 sdd28 sdd29 j v ss v ss sdclk0 sdd30 sdd31 sdcs0# k v ss v ss sdclk1 sdcs1# sdcs2# sdwe# l v ss v ss sdclk2 sdcas# sdcke sdras# m v ss v ss v ddi sdqm2# sdqm1# sdqm0# n v ss v ss v ddx sdba1 sdba0 sdqm3# p v ddx sda2 sda1 sda0 r v ddx sda5 sda4 sda3 t v ddx sda8 sda7 sda6 u sda12 sda11 sda10 sda9 v gpio[7] gpio[6] (smromcke) v ddx v ddx v ddx romsize romsel tms vddxok resetout# w pwe# pior# gpio[5] (dma_req1) tc1 pwr_en gpio[0] xagnd12 xpwr12 testen trst# y pwait# poe# tc3 tc2 gpio[3] (extclk1) tc0 gpio[1] resetin# xagnd32 xpwr32 aa pce2# preg# pios16# piow# gpio[4] (dma_req0) gpio[2] (extclk0) xti12 xto12 xti32 xto32 ab 13 14 15 16 17 18 19 20 21 22
amd alchemy? au1000? processor data book - preliminary 261 packaging, pin assignment and ordering information 30360d table 12-1. pin assignment ? sorted by pin number pin number default signal alternate signal a1 s0dout gpio[16] a2 u2rxd a3 s0clk gpio[17] a4 i2sdio gpio[29] a5 acsync s1dout a6 n0rxd1 a7 n0rxd2 a8 u0txd gpio[20] a9 u2txd gpio[22] a10 n0rxdv a11 n0txen a12 n1txclk a13 n0txd3 a14 n1rxd0 a15 n1rxd1 a16 n0mdio a17 gpio[15] irfirsel a18 n1txen gpio[24] a19 n1txd3 gpio[28] a20 sdd0 a21 sdd3 a22 sdd5 b1 usbh1m b2 usbdm usbh0m b3 u1rxd b4 n0txclk b5 acbclk s1din b6 n0rxd0 b7 i2sclk gpio[30] b8 i2sword gpio[31] b9 u1txd gpio[21] b10 n0rxclk b11 n0col b12 n0txd1 b13 n1crs b14 n0mdc b15 gpio[14] u3dtr b16 n1rxd3 b17 n1txd0 gpio[25] b18 n1rxdv b19 n1mdc b20 sdd1 b21 sdd4 b22 sdd6 c1 gpio[12] u3ri c2 tck c3 usbh1p c4 s0den gpio[18] c5 irdatx gpio[19] c6 n0crs c7 acrst# s1den c8 acdo s1clk c9 n0rxd3 c10 u3txd gpio[23] c11 n0txd0 c12 n0txd2 c13 gpio[13] u3rts c14 n1rxd2 c15 n1rxclk c16 n1txd2 gpio[27] c17 n1txd1 gpio[26] c18 n1col c19 n1mdio c20 sdd2 c21 sdd10 c22 sdd11 d1 tdi d2 gpio[11] u3dcd d3 u0rxd d4 usbdp usbh0p d5 u3rxd d6 acdi d7 v ddx d8 v ddx d9 v ddx d10 v ddi d11 v ddi d12 v ddi d13 v ddi d14 v ddx d15 v ddx d16 v ddx d17 sdd9 d18 sdd8 d19 sdd7 d20 sdd12 d21 sdd13 d22 sdd14 e1 tdo e2 gpio[9] u3cts e3 gpio[10] u3dsr e4 irdarx e19 v ddx e20 sdd15 e21 sdd16 pin number default signal alternate signal
262 amd alchemy? au1000? processor data book - preliminary packaging, pin assignment and ordering information 30360d e22 sdd17 f1 rcs2# f2 rcs3# f3 gpio[8] i2sdi f4 s0din f19 v ddx f20 sdd18 f21 sdd19 f22 sdd20 g1 roe# g2 rcs0# g3 rcs1# g4 v ddx g19 v ddx g20 sdd21 g21 sdd22 g22 sdd23 h1 rben2# h2 rben3# h3 rwe# h4 v ddx h19 v ddi h20 sdd24 h21 sdd25 h22 sdd26 j1 rad31 j2 rben0# j3 rben1# j4 v ddx j9 v ss j10 v ss j11 v ss j12 v ss j13 v ss j14 v ss j19 v ddi j20 sdd27 j21 sdd28 j22 sdd29 k1 rad28 k2 rad29 k3 rad30 k4 v ddi k9 v ss k10 v ss k11 v ss pin number default signal alternate signal k12 v ss k13 v ss k14 v ss k19 sdclk0 k20 sdd30 k21 sdd31 k22 sdcs0# l1 rad25 l2 rad27 l3 rad26 l4 v ddi l9 v ss l10 v ss l11 v ss l12 v ss l13 v ss l14 v ss l19 sdclk1 l20 sdcs1# l21 sdcs2# l22 sdwe# m1 rad23 m2 rad24 m3 rad22 m4 v ddi m9 v ss m10 v ss m11 v ss m12 v ss m13 v ss m14 v ss m19 sdclk2 m20 sdcas# m21 sdcke m22 sdras# n1 rad21 n2 rad20 n3 rad18 n4 v ddx n9 v ss n10 v ss n11 v ss n12 v ss n13 v ss n14 v ss pin number default signal alternate signal table 12-1. pin assignment ? sorted by pin number (continued)
amd alchemy? au1000? processor data book - preliminary 263 packaging, pin assignment and ordering information 30360d n19 v ddi n20 sdqm2# n21 sdqm1# n22 sdqm0# p1 rad19 p2 rad17 p3 rad15 p4 v ddx p9 v ss p10 v ss p11 v ss p12 v ss p13 v ss p14 v ss p19 v ddx p20 sdba1 p21 sdba0 p22 sdqm3# r1 rad16 r2 rad14 r3 rad10 r4 v ddx r19 v ddx r20 sda2 r21 sda1 r22 sda0 t1 rad13 t2 rad12 t3 rad7 t4 v ddx t19 v ddx t20 sda5 t21 sda4 t22 sda3 u1 rad11 u2 rad9 u3 rad4 u4 rad0 u19 v ddx u20 sda8 u21 sda7 u22 sda6 v1 rad8 v2 rad6 v3 rad2 v4 rd23 v19 sda12 pin number default signal alternate signal v20 sda11 v21 sda10 v22 sda9 w1 rad5 w2 rad3 w3 rd30 w4 rd22 w5 rd19 w6 v ddx w7 v ddx w8 v ddx w9 v ddi w10 lclk w11 v ddi w12 v ddi w13 gpio[7] w14 gpio[6] smromcke w15 v ddx w16 v ddx w17 v ddx w18 romsize w19 romsel w20 tms w21 vddxok w22 resetout# y1 rad1 y2 rd31 y3 rd26 y4 rd20 y5 rd16 y6 rd13 y7 rd10 y8 rd7 y9 rd3 y10 lwr1# y11 lrd1# y12 pce1# y13 pwe# y14 pior# y15 gpio[5] dma_req1 y16 tc1 y17 pwr_en y18 gpio[0] y19 xagnd12 y20 xpwr12 y21 testen y22 trst# pin number default signal alternate signal table 12-1. pin assignment ? sorted by pin number (continued)
264 amd alchemy? au1000? processor data book - preliminary packaging, pin assignment and ordering information 30360d aa1 rd29 aa2 rd27 aa3 rd25 aa4 rd18 aa5 rd15 aa6 rd12 aa7 rd9 aa8 rd6 aa9 rd4 aa10 rd0 aa11 lwait# aa12 lrd0# aa13 pwait# aa14 poe# aa15 tc3 aa16 tc2 aa17 gpio[3] extclk1 aa18 tc0 aa19 gpio[1] aa20 resetin# aa21 xagnd32 aa22 xpwr32 pin number default signal alternate signal ab1 rd28 ab2 rd24 ab3 rd21 ab4 rd17 ab5 rd14 ab6 rd11 ab7 rd8 ab8 rd5 ab9 rd2 ab10 rd1 ab11 ewait# ab12 lwr0# ab13 pce2# ab14 preg# ab15 pios16 ab16 piow# ab17 gpio[4] dma_req0 ab18 gpio[2] extclk0 ab19 xti12 ab20 xto12 ab21 xti32 ab22 xto32 pin number default signal alternate signal table 12-1. pin assignment ? sorted by pin number (continued)
amd alchemy? au1000? processor data book - preliminary 265 packaging, pin assignment and ordering information 30360d table 12-2. pin assignment ? sorted alphabetically by default signal default signal alternate signal pin number acbclk s1din b5 acdi d6 acdo s1clk c8 acrst# s1den c7 acsync s1dout a5 ewait# ab11 gpio[0] y18 gpio[1] aa19 gpio[2] extclk0 ab18 gpio[3] extclk1 aa17 gpio[4] dma_req0 ab17 gpio[5] dma_req1 y15 gpio[6] smromcke w14 gpio[7] w13 gpio[8] i2sdi f3 gpio[9] u3cts e2 gpio[10] u3dsr e3 gpio[11] u3dcd d2 gpio[12] u3ri c1 gpio[13] u3rts c13 gpio[14] u3dtr b15 gpio[15] irfirsel a17 i2sclk gpio[30] b7 i2sdio gpio[29] a4 i2sword gpio[31] b8 irdarx e4 irdatx gpio[19] c5 lclk w10 lrd0# aa12 lrd1# y11 lwait# aa11 lwr0# ab12 lwr1# y10 n0col b11 n0crs c6 n0mdc b14 n0mdio a16 n0rxclk b10 n0rxd0 b6 n0rxd1 a6 n0rxd2 a7 n0rxd3 c9 n0rxdv a10 n0txclk b4 n0txd0 c11 n0txd1 b12 n0txd2 c12 n0txd3 a13 n0txen a11 n1col c18 n1crs b13 n1mdc b19 n1mdio c19 n1rxclk c15 n1rxd0 a14 n1rxd1 a15 n1rxd2 c14 n1rxd3 b16 n1rxdv b18 n1txclk a12 n1txd0 gpio[25] b17 n1txd1 gpio[26] c17 n1txd2 gpio[27] c16 n1txd3 gpio[28] a19 n1txen gpio[24] a18 pce1# y12 pce2# ab13 pior# y14 pios16# ab15 piow# ab16 poe# aa14 preg# ab14 pwait# aa13 pwe# y13 pwr_en y17 rad0 u4 rad1 y1 rad2 v3 rad3 w2 rad4 u3 rad5 w1 rad6 v2 rad7 t3 rad8 v1 rad9 u2 rad10 r3 rad11 u1 rad12 t2 rad13 t1 rad14 r2 rad15 p3 rad16 r1 rad17 p2 rad18 n3 rad19 p1 rad20 n2 default signal alternate signal pin number
266 amd alchemy? au1000? processor data book - preliminary packaging, pin assignment and ordering information 30360d rad21 n1 rad22 m3 rad23 m1 rad24 m2 rad25 l1 rad26 l3 rad27 l2 rad28 k1 rad29 k2 rad30 k3 rad31 j1 rben0# j2 rben1# j3 rben2# h1 rben3# h2 rcs0# g2 rcs1# g3 rcs2# f1 rcs3# f2 rd0 aa10 rd1 ab10 rd2 ab9 rd3 y9 rd4 aa9 rd5 ab8 rd6 aa8 rd7 y8 rd8 ab7 rd9 aa7 rd10 y7 rd11 ab6 rd12 aa6 rd13 y6 rd14 ab5 rd15 aa5 rd16 y5 rd17 ab4 rd18 aa4 rd19 w5 rd20 y4 rd21 ab3 rd22 w4 rd23 v4 rd24 ab2 rd25 aa3 rd26 y3 rd27 aa2 rd28 ab1 default signal alternate signal pin number rd29 aa1 rd30 w3 rd31 y2 resetin# aa20 resetout# w22 roe# g1 romsel w19 romsize w18 rwe# h3 s0clk gpio[17] a3 s0den gpio[18] c4 s0din f4 s0dout gpio[16] a1 sda0 r22 sda1 r21 sda2 r20 sda3 t22 sda4 t21 sda5 t20 sda6 u22 sda7 u21 sda8 u20 sda9 v22 sda10 v21 sda11 v20 sda12 v19 sdba0 p21 sdba1 p20 sdcas# m20 sdcke m21 sdclk0 k19 sdclk1 l19 sdclk2 m19 sdcs0# k22 sdcs1# l20 sdcs2# l21 sdd0 a20 sdd1 b20 sdd2 c20 sdd3 a21 sdd4 b21 sdd5 a22 sdd6 b22 sdd7 d19 sdd8 d18 sdd9 d17 sdd10 c21 sdd11 c22 default signal alternate signal pin number table 12-2. pin assignment ? sorted alph abetically by default signal (continued)
amd alchemy? au1000? processor data book - preliminary 267 packaging, pin assignment and ordering information 30360d sdd12 d20 sdd13 d21 sdd14 d22 sdd15 e20 sdd16 e21 sdd17 e22 sdd18 f20 sdd19 f21 sdd20 f22 sdd21 g20 sdd22 g21 sdd23 g22 sdd24 h20 sdd25 h21 sdd26 h22 sdd27 j20 sdd28 j21 sdd29 j22 sdd30 k20 sdd31 k21 sdqm0# n22 sdqm1# n21 sdqm2# n20 sdqm3# p22 sdras# m22 sdwe# l22 tc0 aa18 tc1 y16 tc2 aa16 tc3 aa15 tck c2 tdi d1 tdo e1 testen y21 tms w20 trst# y22 u0rxd d3 u0txd gpio[20] a8 u1rxd b3 default signal alternate signal pin number u1txd gpio[21] b9 u2rxd a2 u2txd gpio[22] a9 u3rxd d5 u3txd gpio[23] c10 usbdm usbh0m b2 usbdp usbh0p d4 usbh1m b1 usbh1p c3 v ddi (total of 13) d10, d11, d12, d13, h19, j19, k4, l4, m4, n19, w9, w11, w12 v ddx (total of 26) d7, d8, d9, d14, d15, d16, e19, f19, g4, g19, h4, j4, n4, p4, p19, r4, r19, t4, t19, u19, w6, w7, w8, w15, w16, w17 vddxok w21 v ss (total of 36) j9, j10, j11, j12, j13, j14, k9, k10, k11, k12, k13, k14, l9, l10, l11, l12, l13, l14, m9, m10, m11, m12, m13, m14, n9, n10, n11, n12, n13, n14, p9, p10, p11, p12, p13, p14 xagnd12 y19 xagnd32 aa21 xpwr12 y20 xpwr32 aa22 xti12 ab19 xti32 ab21 xto12 ab20 xto32 ab22 default signal alternate signal pin number table 12-2. pin assignment ? sorted alph abetically by default signal (continued)
268 amd alchemy? au1000? processor data book - preliminary packaging, pin assignment and ordering information 30360d table 12-3. pin assignment ? alternate signals sorted alphabetically alternate signal default signal pin number dma_req0 gpio[4] ab17 dma_req1 gpio[5] y15 extclk0 gpio[2] ab18 extclk1 gpio[3] aa17 gpio[16] s0dout a1 gpio[17] s0clk a3 gpio[18] s0den c4 gpio[19] irdatx c5 gpio[20] u0txd a8 gpio[21] u1txd b9 gpio[22] u2txd a9 gpio[23] u3txd c10 gpio[24] n1txen a18 gpio[25] n1txd0 b17 gpio[26] n1txd1 c17 gpio[27] n1txd2 c16 gpio[28] n1txd3 a19 gpio[29] i2sdio a4 gpio[30] i2sclk b7 gpio[31] i2sword b8 i2sdi gpio[8] f3 irfirsel gpio[15] a17 s1clk acdo c8 s1den acrst# c7 s1din acbclk b5 s1dout acsync a5 smromcke gpio[6] w14 u3cts gpio[9] e2 u3dcd gpio[11] d2 u3dsr gpio[10] e3 u3dtr gpio[14] b15 u3ri gpio[12] c1 u3rts gpio[13] c13 usbh0m usbdm b2 usbh0p usbdp d4
amd alchemy? au1000? processor data book - preliminary 269 packaging, pin assignment and ordering information 30360d 12.3 ordering information valid combinations au1000-266 au1000-400 au1000-500 mc c valid combinations valid combinations lists configurations planned to be supported in volume for this device. consult the local amd sales office to confirm availability of specific valid combinations and to check on newly released combinations. au1000-266 mc i temperature range c = commercial (ta = 0 { c to +70 { c, where ta= ambient temperature) i = industrial (ta = -40 { c to +85 { c) package type mc = low profile pbga package (1mm ball-pitch) speed option 266 = 266mhz 400 = 400mhz 500 = 500mhz device number/description au1000 - 266 mc c
270 amd alchemy? au1000? processor data book - preliminary packaging, pin assignment and ordering information 30360d
a amd alchemy? au1000? processor data book - preliminary 271 appendix a: support documentation 30360d appendix a support documentation a.1 memory map the peripheral devices on the au1000 processor contain memory-mapped registers visible to software. table a-1 contains the memory map for the peripheral devices and physical memory. the addresses are 36 bits wide. the au1000 processor system bus devices are mapped at the addresses based at 0x0_1400_0000. see table a-2 for complete addresses. table a-1. basic au1000? processor physical memory map start address end address size (mb) function 0x0_0000_0000 0x0_0fff_ffff 256 memory kseg 0/1 0x0_1000_0000 0x0_11ff_ffff 32 i/o devices on peripheral bus 0x0_1200_0000 0x0_13ff_ffff 32 reserved 0x0_1400_0000 0x0_17ff_ffff 64 i/o devices on system bus 0x0_1800_0000 0x0_1fff_ffff 128 memory mapped. 0x0_1fc00000 must contain the boot vector so this is typically where flash or rom is located. 0x0_2000_0000 0x0_7fff_ffff 1536 memory mapped 0x0_8000_0000 0x0_efff_ffff 1792 memory mapp ed. currently this space is memory mapped, but it should be considered reserved for future use. 0x0_f000_0000 0x0_ffff_ffff 256 debug probe 0x1 0000_0000 0xc ffff_ffff 4096 * 12 reserved 0xd 0000_0000 0xd ffff_ffff 4096 i/o device 0xe 0000_0000 0xe ffff_ffff 4096 external lcd controller interface 0xf 0000_0000 0xf ffff_ffff 4096 pcmcia interface table a-2. system bus devices physical memory map start address end address size function 0x0_1400_0000 0x0_14000_fff 4 kb sdram memory controller 0x0_1400_1000 0x0_1400_1fff 4 kb sram/flash memory controller 0x0_1400_2000 0x0_1400_2fff 4 kb dma 0x0_1400_4000 0x0_1400_4fff 4 kb ethernet dma
272 amd alchemy? au1000? processor data book - preliminary appendix a: memory map 30360d the au1000 processor peripheral bus devices are based at 0x 0_11000000. the individual memory spaces of the devices are defined in table a-3. table a-3. peripheral bus devices physical memory map start address end address size function 0x0_1000_0000 0x0_100f_ffff 1 mb ac97 controller 0x0_1010_0000 0x0_101f_ffff 1 mb usb host 0x0_1020_0000 0x0_102f_ffff 1 mb usb device 0x0_1030_0000 0x0_103f_ffff 1 mb irda 0x0_1040_0000 0x0_104f_ffff 1 mb interrupt controller 0 0x0_1050_0000 0x0_105f_ffff 1 mb ethernet mac 0x0_1060_0000 0x0_10ff_ffff 10 mb 0x0_1100_0000 0x0_110f_ffff 1 mb i 2 s 0x0_1110_0000 0x0_111f_ffff 1 mb uart0 0x0_1120_0000 0x0_112f_ffff 1 mb uart1 0x0_1130_0000 0x0_113f_ffff 1 mb uart2 0x0_1140_0000 0x0_114f_ffff 1 mb uart3 0x0_1150_0000 0x0_115f_ffff 1 mb 0x0_1160_0000 0x0_116f_ffff 1 mb ssi 0x0_1170_0000 0x0_117f_ffff 1 mb 0x0_1180_0000 0x0_118f_ffff 1 mb interrupt controller 1 0x0_1190_0000 0x0_119f_ffff 1 mb system control. rtc, toy, timers, primary gpio, power management
amd alchemy? au1000? processor data book - preliminary 273 appendix a: memory map 30360d a.1.1 device memory map table a-4 lists all of the devices that are memory mapped to the au1000 processor core. these devices are all mapped within kseg1 (non-cached, non-tlb). all 32-b it addresses are translated into 36-bit addresses by changing bits 31:29 to zero and adding bits 35:32 which are set to zero. table a-4. device memory map register kseg1 address physical address ac97 controller - section 6.1 ac97_config 0x_b000_0000 0x0_1000_0000 ac97_status 0x_b000_0004 0x0_1000_0004 ac97_data 0x_b000_0008 0x0_1000_0008 ac97_cmmd 0x_b000_000c 0x0_1000_000c ac97_cmmdresp 0x_b000_000c 0x0_1000_000c ac97_control 0x_b000_0010 0x0_1000_0010 usb host controller - section 6.2 open hci register set base 0x_b010_0000 0x0_1010_0000 usbh_enable 0x_b017_fffc 0x0_1017_fffc usb device controller - section 6.3 usbd_ep0rd 0x_b020_0000 0x0_1020_0000 usbd_ep0wr 0x_b020_0004 0x0_1020_0004 usbd_ep1wr 0x_b020_0008 0x0_1020_0008 usbd_ep2wr 0x_b020_000c 0x0_1020_000c usbd_ep3rd 0x_b020_0010 0x0_1020_0010 usbd_ep4rd 0x_b020_0014 0x0_1020_0014 usbd_inten 0x_b020_0018 0x0_1020_0018 usbd_intstat 0x_b020_001c 0x0_1020_001c usbd_config 0x_b020_0020 0x0_1020_0020 usbd_ep0cs 0x_b020_0024 0x0_1020_0024 usbd_ep1cs 0x_b020_0028 0x0_1020_0028 usbd_ep2cs 0x_b020_002c 0x0_1020_002c usbd_ep3cs 0x_b020_0030 0x0_1020_0030 usbd_ep4cs 0x_b020_0034 0x0_1020_0034 usbd_ep0rdstat 0x_b020_0040 0x0_1020_0040 usbd_ep0wrstat 0x_b020_0044 0x0_1020_0044 usbd_ep1wrstat 0x_b020_0048 0x0_1020_0048 usbd_ep2wrstat 0x_b020_004c 0x0_1020_004c usbd_ep3rdstat 0x_b020_0050 0x0_1020_0050 usbd_ep4rdstat 0x_b020_0054 0x0_1020_0054 usbd_enable 0x_b020_0058 0x0_1020_0058 irda controller - section 6.4 ir_rngptrstat 0x_b030_0000 0x0_1030_0000 ir_rngbsadrh 0x_b030_0004 0x0_1030_0004 ir_rngbsadrl 0x_b030_0008 0x0_1030_0008 ir_ringsize 0x_b030_000c 0x0_1030_000c ir_rngprompt 0x_b030_0010 0x0_1030_0010 ir_rngadrcmp 0x_b030_0014 0x0_1030_0014 ir_intclear 0x_b030_0018 0x0_1030_0018 ir_config1 0x_b030_0020 0x0_1030_0020 ir_sirflags 0x_b030_0024 0x0_1030_0024 ir_statusen 0x_b030_0028 0x0_1030_0028 ir_rdphycfg 0x_b030_002c 0x0_1030_002c ir_wrphycfg 0x_b030_0030 0x0_1030_0030 ir_maxpktlen 0x_b030_0034 0x0_1030_0034 ir_rxbytecnt 0x_b030_0038 0x0_1030_0038 ir_config2 0x_b030_003c 0x0_1030_003c ir_enable 0x_b030_0040 0x0_1030_0040 interrupt controller 0 - section 5.0 ic0_cfg0rd 0x_b040_0040 0x0_1040_0040 ic0_cfg0set 0x_b040_0040 0x0_1040_0040 ic0_cfg0clr 0x_b040_0044 0x0_1040_0044 ic0_cfg1rd 0x_b040_0048 0x0_1040_0048 ic0_cfg1set 0x_b040_0048 0x0_1040_0048 ic0_cfg1clr 0x_b040_004c 0x0_1040_004c ic0_cfg2rd 0x_b040_0050 0x0_1040_0050 ic0_cfg2set 0x_b040_0050 0x0_1040_0050 ic0_cfg2clr 0x_b040_0054 0x0_1040_0054 ic0_req0int 0x_b040_0054 0x0_1040_0054 ic0_srcrd 0x_b040_0058 0x0_1040_0058 ic0_srcset 0x_b040_0058 0x0_1040_0058 ic0_srcclr 0x_b040_005c 0x0_1040_005c ic0_req1int 0x_b040_005c 0x0_1040_005c ic0_assignrd 0x_b040_0060 0x0_1040_0060 ic0_assignset 0x_b040_0060 0x0_1040_0060 ic0_assignclr 0x _b040_0064 0x0_1040_0064 ic0_wakerd 0x_b040_0068 0x0_1040_0068 ic0_wakeset 0x_b040_006c 0x0_1040_006c ic0_wakeclr 0x_b040_0070 0x0_1040_0070 ic0_maskrd 0x_b040_0070 0x0_1040_0070 ic0_maskset 0x_b040_0074 0x0_1040_0074 ic0_maskclr 0x_b040_0078 0x0_1040_0078 ic0_risingrd 0x_b040_0078 0x0_1040_0078 ic0_risingclr 0x_b040_007c 0x0_1040_007c ic0_fallingrd 0x_b040_007c 0x0_1040_007c ic0_fallingclr 0x_b040_0080 0x0_1040_0080 ethernet controller mac0 - section 6.5 mac0_control 0x_b050_0000 0x0_1050_0000 mac0_addrhigh 0x_b050_0004 0x0_1050_0004 mac0_addrlow 0x_b050_0008 0x0_1050_0008 mac0_hashhigh 0x_b050_000c 0x0_1050_000c mac0_hashlow 0x_b050_0010 0x0_1050_0010 mac0_miictrl 0x_b050_0014 0x0_1050_0014 mac0_miidata 0x_b050_0018 0x0_1050_0018 register kseg1 address physical address
274 amd alchemy? au1000? processor data book - preliminary appendix a: memory map 30360d mac0_flowctrl 0x_b050_001c 0x0_1050_001c mac0_vlan1 0x_b050_0020 0x0_1050_0020 mac0_vlan2 0x_b050_0024 0x0_1050_0024 ethernet controller mac1 - section 6.5 mac1_control 0x_b051_0000 0x0_1051_0000 mac1_addrhigh 0x_b051_0004 0x0_1051_0004 mac1_addrlow 0x_b051_0008 0x0_1051_0008 mac1_hashhigh 0x_b051_000c 0x0_1051_000c mac1_hashlow 0x_b051_0010 0x0_1051_0010 mac1_miictrl 0x_b051_0014 0x0_1051_0014 mac1_miidata 0x_b051_0018 0x0_1051_0018 mac1_flowctrl 0x_b051_001c 0x0_1051_001c mac1_vlan1 0x_b051_0020 0x0_1051_0020 mac1_vlan2 0x_b051_0024 0x0_1051_0024 ethernet controller enable - section 6.5 macen_mac0 0x_b052_0000 0x0_1052_0000 macen_mac1 0x_b052_0004 0x0_1052_0004 i 2 s controller section 6.6 i2s_data 0x_b100_0000 0x0_1100_0000 i2s_config 0x_b100_0004 0x0_1100_0004 i2s_enable 0x_b100_0008 0x0_1100_0008 uart0 - section 6.7 uart0_rxdata 0x_b110_0000 0x0_1110_0000 uart0_txdata 0x_b110_0004 0x0_1110_0004 uart0_inten 0x_b110_0008 0x0_1110_0008 uart0_intcause 0x_b110_000c 0x0_1110_000c uart0_fifoctrl 0x_b110_0010 0x0_1110_0010 uart0_linectrl 0x_b110_0014 0x0_1110_0014 ? 0x_b110_0018 0x0_1110_0018 uart0_linestat 0x_b110_001c 0x0_1110_001c ? 0x_b110_0020 0x0_1110_0020 uart0_clkdiv 0x_b110_0028 0x0_1110_0028 uart0_enable 0x_b110_0100 0x0_1110_0100 uart1 - section 6.7 uart1_rxdata 0x_b120_0000 0x0_1120_0000 uart1_txdata 0x_b120_0004 0x0_1120_0004 uart1_inten 0x_b120_0008 0x0_1120_0008 uart1_intcause 0x_b120_000c 0x0_1120_000c uart1_fifoctrl 0x_b120_0010 0x0_1120_0010 uart1_linectrl 0x_b120_0014 0x0_1120_0014 ? 0x_b120_0018 0x0_1120_0018 uart1_linestat 0x_b120_001c 0x0_1120_001c ? 0x_b120_0020 0x0_1120_0020 uart1_clkdiv 0x_b120_0028 0x0_1120_0028 uart1_enable 0x_b120_0100 0x0_1120_0100 uart2 - section 6.7 uart2_rxdata 0x_b130_0000 0x0_1130_0000 register kseg1 address physical address uart2_txdata 0x_b130_0004 0x0_1130_0004 uart2_inten 0x_b130_0008 0x0_1130_0008 uart2_intcause 0x_b130_000c 0x0_1130_000c uart2_fifoctrl 0x_b130_0010 0x0_1130_0010 uart2_linectrl 0x_b130_0014 0x0_1130_0014 ? 0x_b130_0018 0x0_1130_0018 uart2_linestat 0x_b130_001c 0x0_1130_001c ? 0x_b130_0020 0x0_1130_0020 uart2_clkdiv 0x_b130_0028 0x0_1130_0028 uart2_enable 0x_b130_0100 0x0_1130_0100 uart3 - section 6.7 uart3_rxdata 0x_b140_0000 0x0_1140_0000 uart3_txdata 0x_b140_0004 0x0_1140_0004 uart3_inten 0x_b140_0008 0x0_1140_0008 uart3_intcause 0x_b140_000c 0x0_1140_000c uart3_fifoctrl 0x_b140_0010 0x0_1140_0010 uart3_linectrl 0x_b140_0014 0x0_1140_0014 uart3_mdmctrl 0x_b140_0018 0x0_1140_0018 uart3_linestat 0x_b140_001c 0x0_1140_001c uart3_mdmstat 0x_b140_0020 0x0_1140_0020 uart3_autoflow 0x_b140_0024 0x0_1140_0024 uart3_clkdiv 0x_b140_0028 0x0_1140_0028 uart3_enable 0x_b140_0100 0x0_1140_0100 ssi0 - section 6.8 ssi0_status 0x_b160_0000 0x0_1160_0000 ssi0_int 0x_b160_0004 0x0_1160_0004 ssi0_inten 0x_b160_0008 0x0_1160_0008 ssi0_config 0x_b160_0020 0x0_1160_0020 ssi0_adata 0x_b160_0024 0x0_1160_0024 ssi0_clkdiv 0x_b160_0028 0x0_1160_0028 ssi0_enable 0x_b160_0100 0x0_1160_0100 ssi1- section 6.8 ssi1_status 0x_b168_0000 0x0_1168_0000 ssi1_int 0x_b168_0004 0x0_1168_0004 ssi1_inten 0x_b168_0008 0x0_1168_0008 ssi1_config 0x_b168_0020 0x0_1168_0020 ssi1_adata 0x_b168_0024 0x0_1168_0024 ssi1_clkdiv 0x_b168_0028 0x0_1168_0028 ssi1_enable 0x_b168_0100 0x0_1168_0100 interrupt controller 1 - section 5.0 ic1_cfg0rd 0x_b180_0040 0x0_1180_0040 ic1_cfg0set 0x_b180_0040 0x0_1180_0040 ic1_cfg0clr 0x_b180_0044 0x0_1180_0044 ic1_cfg1rd 0x_b180_0048 0x0_1180_0048 ic1_cfg1set 0x_b180_0048 0x0_1180_0048 ic1_cfg1clr 0x_b180_004c 0x0_1180_004c ic1_cfg2rd 0x_b180_0050 0x0_1180_0050 ic1_cfg2set 0x_b180_0050 0x0_1180_0050 register kseg1 address physical address table a-4. device memory map (continued)
amd alchemy? au1000? processor data book - preliminary 275 appendix a: memory map 30360d ic1_cfg2clr 0x_b180_0054 0x0_1180_0054 ic1_req0int 0x_b180_0054 0x0_1180_0054 ic1_srcrd 0x_b180_0058 0x0_1180_0058 ic1_srcset 0x_b180_0058 0x0_1180_0058 ic1_srcclr 0x_b180_005c 0x0_1180_005c ic1_req1int 0x_b180_005c 0x0_1180_005c ic1_assignrd 0x_b180_0060 0x0_1180_0060 ic1_assignset 0x_b180_0060 0x0_1180_0060 ic1_assignclr 0x_b180_0064 0x0_1180_0064 ic1_wakerd 0x_b180_0068 0x0_1180_0068 ic1_wakeset 0x_b180_006c 0x0_1180_006c ic1_wakeclr 0x_b180_0070 0x0_1180_0070 ic1_maskrd 0x_b180_0070 0x0_1180_0070 ic1_maskset 0x_b180_0074 0x0_1180_0074 ic1_maskclr 0x_b180_0078 0x0_1180_0078 ic1_risingrd 0x_b180_0078 0x0_1180_0078 ic1_risingclr 0x_b180_007c 0x0_1180_007c ic1_fallingrd 0x_b180_007c 0x0_1180_007c ic1_fallingclr 0x_b180_0080 0x0_1180_0080 clock controller - section 7.1 sys_freqctrl0 0x_b190_0020 0x0_1190_0020 sys_freqctrl1 0x_b190_0024 0x0_1190_0024 sys_clksrc 0x_b190_0028 0x0_1190_0028 sys_cpupll 0x_b190_0060 0x0_1190_0060 sys_auxpll 0x_b190_0064 0x0_1190_0064 toy & rtc - section 7.2 sys_toytrim 0x_b190_0000 0x0_1190_0000 sys_toywrite 0x_b190_0004 0x0_1190_0004 sys_matchtoy0 0x_b190_0008 0x0_1190_0008 sys_matchtoy1 0x_b190_000c 0x0_1190_000c sys_matchtoy2 0x_b190_0010 0x0_1190_0010 sys_cntrctrl 0x_b190_0014 0x0_1190_0014 sys_toyread 0x_b190_0040 0x0_1190_0040 sys_rtctrim 0x_b190_0044 0x0_1190_0044 sys_rtcwrite 0x_b190_0048 0x0_1190_0048 sys_rtcmatch0 0x_b190_004c 0x0_1190_004c sys_rtcmatch1 0x_b190_0050 0x0_1190_0050 sys_rtcmatch2 0x_b190_0054 0x0_1190_0054 sys_rtcread 0x_b190_0058 0x0_1190_0058 gpio - section 7.3 sys_pinfunc 0x_b190_002c 0x0_1190_002c sys_trioutrd 0x_b190_0100 0x0_1190_0100 sys_trioutclr 0x_b190_0100 0x0_1190_0100 sys_outputrd 0x_b190_0108 0x0_1190_0108 sys_outputset 0x_b190_0108 0x0_1190_0108 sys_outputclr 0x_b190_010c 0x0_1190_010c sys_pinstaterd 0x_b190_0110 0x0_1190_0110 sys_pininputen 0x_b190_0110 0x0_1190_0110 register kseg1 address physical address power management - section 7.4 sys_scratch0 0x_b190_0018 0x0_1190_0018 sys_scratch1 0x_b190_001c 0x0_1190_001c sys_wakemsk 0x_b190_0034 0x0_1190_0034 sys_endian 0x_b190_0038 0x0_1190_0038 sys_powerctrl 0x_b190_003c 0x0_1190_003c sys_wakesrc 0x_b190_005c 0x0_1190_005c sys_slppwr 0x_b190_0078 0x0_1190_0078 sys_sleep 0x_b190_007c 0x0_1190_007c sdram controller - section 3.1 mem_sdmode0 0x_b400_0000 0x0_1400_0000 mem_sdmode1 0x_b400_0004 0x0_1400_0004 mem_sdmode2 0x_b400_0008 0x0_1400_0008 mem_sdaddr0 0x_b400_000c 0x0_1400_000c mem_sdaddr1 0x_b400_0010 0x0_1400_0010 mem_sdaddr2 0x_b400_0014 0x0_1400_0014 mem_sdrefcfg 0x_b400_0018 0x0_1400_0018 mem_sdprecmd 0x_b400_001c 0x0_1400_001c mem_sdautoref 0x_b400_0020 0x0_1400_0020 mem_sdwrmd0 0x_b400_0024 0x0_1400_0024 mem_sdwrmd1 0x_b400_0028 0x0_1400_0028 mem_sdwrmd2 0x_b400_002c 0x0_1400_002c mem_sdsleep 0x_b400_0030 0x0_1400_0030 mem_sdsmcke 0x_b400_0034 0x0_1400_0034 static bus controller - section 3.2 mem_stcfg0 0x_b400_1000 0x0_1400_1000 mem_sttime0 0x_b400_1004 0x0_1400_1004 mem_staddr0 0x_b400_1008 0x0_1400_1008 mem_stcfg1 0x_b400_1010 0x0_1400_1010 mem_sttime1 0x_b400_1014 0x0_1400_1014 mem_staddr1 0x_b400_1018 0x0_1400_1018 mem_stcfg2 0x_b400_1020 0x0_1400_1020 mem_sttime2 0x_b400_1024 0x0_1400_1024 mem_staddr2 0x_b400_1028 0x0_1400_1028 mem_stcfg3 0x_b400_1030 0x0_1400_1030 mem_sttime3 0x_b400_1034 0x0_1400_1034 mem_staddr3 0x_b400_1038 0x0_1400_1038 dma controller 0 - section 4.0 dma0_moderead 0x_b400_2000 0x0_1400_2000 dma0_modeset 0x_b400_2000 0x0_1400_2000 dma0_modeclr 0x_b400_2004 0x0_1400_2004 dma0_peraddr 0x_b400_2008 0x0_1400_2008 dma0_buf0addr 0x_b400_200c 0x0_1400_200c dma0_buf0size 0x_b400_2010 0x0_1400_2010 dma0_buf1addr 0x_b400_2014 0x0_1400_2014 dma0_buf1size 0x_b400_2018 0x0_1400_2018 register kseg1 address physical address table a-4. device memory map (continued)
276 amd alchemy? au1000? processor data book - preliminary appendix a: memory map 30360d dma controller 1 - section 4.0 dma1_moderead 0x_b400_2100 0x0_1400_2100 dma1_modeset 0x_b400_2100 0x0_1400_2100 dma1_modeclr 0x_b400_2104 0x0_1400_2104 dma1_peraddr 0x_b400_2108 0x0_1400_2108 dma1_buf0addr 0x_b400_210c 0x0_1400_210c dma1_buf0size 0x_b400_2110 0x0_1400_2110 dma1_buf1addr 0x_b400_2114 0x0_1400_2114 dma1_buf1size 0x_b400_2118 0x0_1400_2118 dma controller 2 - section 4.0 dma2_moderead 0x_b400_2200 0x0_1400_2200 dma2_modeset 0x_b400_2200 0x0_1400_2200 dma2_modeclr 0x_b400_2204 0x0_1400_2204 dma2_peraddr 0x_b400_2208 0x0_1400_2208 dma2_buf0addr 0x_b400_220c 0x0_1400_220c dma2_buf0size 0x_b400_2210 0x0_1400_2210 dma2_buf1addr 0x_b400_2214 0x0_1400_2214 dma2_buf1size 0x_b400_2218 0x0_1400_2218 dma controller 3 - section 4.0 dma3_moderead 0x_b400_2300 0x0_1400_2300 dma3_modeset 0x_b400_2300 0x0_1400_2300 dma3_modeclr 0x_b400_2304 0x0_1400_2304 dma3_peraddr 0x_b400_2308 0x0_1400_2308 dma3_buf0addr 0x_b400_230c 0x0_1400_230c dma3_buf0size 0x_b400_2310 0x0_1400_2310 dma3_buf1addr 0x_b400_2314 0x0_1400_2314 dma3_buf1size 0x_b400_2318 0x0_1400_2318 dma controller 4 - section 4.0 dma4_moderead 0x_b400_2400 0x0_1400_2400 dma4_modeset 0x_b400_2400 0x0_1400_2400 dma4_modeclr 0x_b400_2404 0x0_1400_2404 dma4_peraddr 0x_b400_2408 0x0_1400_2408 dma4_buf0addr 0x_b400_240c 0x0_1400_240c dma4_buf0size 0x_b400_2410 0x0_1400_2410 dma4_buf1addr 0x_b400_2414 0x0_1400_2414 dma4_buf1size 0x_b400_2418 0x0_1400_2418 dma controller 5 - section 4.0 dma5_moderead 0x_b400_2500 0x0_1400_2500 dma5_modeset 0x_b400_2500 0x0_1400_2500 dma5_modeclr 0x_b400_2504 0x0_1400_2504 dma5_peraddr 0x_b400_2508 0x0_1400_2508 dma5_buf0addr 0x_b400_250c 0x0_1400_250c dma5_buf0size 0x_b400_2510 0x0_1400_2510 dma5_buf1addr 0x_b400_2514 0x0_1400_2514 dma5_buf1size 0x_b400_2518 0x0_1400_2518 dma controller 6 - section 4.0 dma6_moderead 0x_b400_2600 0x0_1400_2600 dma6_modeset 0x_b400_2600 0x0_1400_2600 register kseg1 address physical address dma6_modeclr 0x_b400_2604 0x0_1400_2604 dma6_peraddr 0x_b400_2608 0x0_1400_2608 dma6_buf0addr 0x_b400_260c 0x0_1400_260c dma6_buf0size 0x_b400_2610 0x0_1400_2610 dma6_buf1addr 0x_b400_2614 0x0_1400_2614 dma6_buf1size 0x_b400_2618 0x0_1400_2618 dma controller 7 - section 4.0 dma7_moderead 0x_b400_2700 0x0_1400_2700 dma7_modeset 0x_b400_2700 0x0_1400_2700 dma7_modeclr 0x_b400_2704 0x0_1400_2704 dma7_peraddr 0x_b400_2708 0x0_1400_2708 dma7_buf0addr 0x_b400_270c 0x0_1400_270c dma7_buf0size 0x_b400_2710 0x0_1400_2710 dma7_buf1addr 0x_b400_2714 0x0_1400_2714 dma7_buf1size 0x_b400_2718 0x0_1400_2718 ethernet controller dma channels - section 6.5 macdma0_tx0stat 0x_b400_4000 0x0_1400_4000 macdma0_tx0addr 0x_b400_4004 0x0_1400_4004 macdma0_tx0len 0x_b400_4008 0x0_1400_4008 macdma0_tx1stat 0x_b400_4010 0x0_1400_4010 macdma0_tx1addr 0x_b400_4014 0x0_1400_4014 macdma0_tx1len 0x_b400_4018 0x0_1400_4018 macdma0_tx2stat 0x_b400_4020 0x0_1400_4020 macdma0_tx2addr 0x_b400_4024 0x0_1400_4024 macdma0_tx2len 0x_b400_4028 0x0_1400_4028 macdma0_tx3stat 0x_b400_4030 0x0_1400_4030 macdma0_tx3addr 0x_b400_4034 0x0_1400_4034 macdma0_tx3len 0x_b400_4038 0x0_1400_4038 macdma0_rx0stat 0x_b400_4100 0x0_1400_4100 macdma0_rx0addr 0x_b400_4104 0x0_1400_4104 macdma0_rx1stat 0x_b400_4110 0x0_1400_4110 macdma0_rx1addr 0x_b400_4114 0x0_1400_4114 macdma0_rx2stat 0x_b400_4120 0x0_1400_4120 macdma0_rx2addr 0x_b400_4124 0x0_1400_4124 macdma0_rx3stat 0x_b400_4130 0x0_1400_4130 macdma0_rx3addr 0x_b400_4134 0x0_1400_4134 macdma1_tx0stat 0x_b400_4200 0x0_1400_4200 macdma1_tx0addr 0x_b400_4204 0x0_1400_4204 macdma1_tx0len 0x_b400_4208 0x0_1400_4208 macdma1_tx1stat 0x_b400_4210 0x0_1400_4210 macdma1_tx1addr 0x_b400_4214 0x0_1400_4214 macdma1_tx1len 0x_b400_4218 0x0_1400_4218 macdma1_tx2stat 0x_b400_4220 0x0_1400_4220 macdma1_tx2addr 0x_b400_4224 0x0_1400_4224 macdma1_tx2len 0x_b400_4228 0x0_1400_4228 macdma1_tx3stat 0x_b400_4230 0x0_1400_4230 macdma1_tx3addr 0x_b400_4234 0x0_1400_4234 macdma1_tx3len 0x_b400_4238 0x0_1400_4238 register kseg1 address physical address table a-4. device memory map (continued)
amd alchemy? au1000? processor data book - preliminary 277 appendix a: memory map 30360d a.1.2 programming tips a.1.2.1 memory mapped registers peripheral, or system device registers should all be marked with the cca bits to non-cacheable. access must be on 32-bit boundaries, one 32-bit value at a time. see section 2.2 "caches" on page 15 for more information. macdma1_rx0stat 0x_b400_4300 0x0_1400_4300 macdma1_rx0addr 0x_b400_4304 0x0_1400_4304 macdma1_rx1stat 0x_b400_4310 0x0_1400_4310 macdma1_rx1addr 0x_b400_4314 0x0_1400_4314 macdma1_rx2stat 0x_b400_4320 0x0_1400_4320 macdma1_rx2addr 0x_b400_4324 0x0_1400_4324 macdma1_rx3stat 0x_b400_4330 0x0_1400_4330 macdma1_rx3addr 0x_b400_4334 0x0_1400_4334 register kseg1 address physical address table a-4. device memory map (continued)
278 amd alchemy? au1000? processor data book - preliminary appendix a: databook notations 30360d a.2 databook notations this section addresses some of the terminology used in this book. 12.3.1 unpredictable and undefined the terms unpredictable and undefined are used throughout this book to describe the behavior of the processor in certain cases. undefined behavior or operations can occur only as the result of executing instructions in a privileged mode (i.e., in kernel mode or debug mode, or with the cp0 usab le bit set in the status register). unprivileged software can never cause undefined behavior or operations. converse ly, both privileged and unprivileged software can cause unpredictable results or operations. 12.3.2 unpredictable unpredictable results may vary from processor implementation to implementation, instruction to instruction, or as a function of time on the same implementat ion or instruction. software can ne ver depend on results that are unpredict- able. unpredictable operations may cause a result to be generat ed or not. if a result is generated, it is unpredict- able. unpredictable operations may cause arbitrary exceptions. unpredictable results or operations have several implementation restrictions: implementations of operations generating unpredictable results must not depend on any data source (memory or internal state) which is inaccessible in the current processor mode unpredictable operations must not read, write, or modify the contents of memory or internal state which is inacces- sible in the current processor mode. for example, unpredictable operations executed in user mode must not access memory or internal state that is only accessibl e in kernel mode or debug mode or in another process unpredictable operations must not halt or hang the processor unpred used to describe the default state of regi sters should be taken as meaning unpredicatable. 12.3.3 undefined undefined operations or behavior may vary from processor im plementation to implementation, instruction to instruction, or as a function of time on the same implementation or instruction. undefined operations or behavior may vary from nothing to creating an environment in wh ich execution can no longer continue. undefined operations or behavior may cause data loss. undefined operations or behavior has one implementation restriction: undefined operations or behavior must not cause the processo r to hang (that is, enter a st ate from which there is no exit other than powering down the processor). the assertion of any of the reset signals must restore the processor to an operational state. 12.3.4 register fields in general, fields marked as reserved should be considered unpredictable. in other words, these fields should be written zeros and ignored on read to preserve future compatibility.
amd alchemy? au1000? processor data book - preliminary 279 appendix a: data book revision history 30360d a.3 data book revision history this document is a report of the revisi on/creation process of the data book for t he au1000 processor. any revisions (i.e., additions, deletions, parameter corrections, etc.) are recorded in the table(s) below. table a-5. revision history revision (date) description a see the amd alchemy? au1000? processor specification update (publication id 27348). b c (june 2005) see revision c for details. d (september 2005) reformatted to bring page count down (from 374 to 281) and correct so me minor errors. see table a-6 for details. table a-6. edits to current revision section revisions / comments all sections / general reformatted document for page, figure, table and section titles. ? all registers now have either a heading 3 or 4 associated with it so the electronic pdf will be more useful. changed active low signals to use and ?#? instead of an overbar (e.g., acrst changed to acrst#). changed the callout format for all physical and ksegx address (e.g., what was 0x0 1400 0000 is now 0x0_1400_0000 and what was 0xb400 000 is now 0x_b400_0000). omitted index and added back cover page. section 1.0 "overview" figure 1-1 "au1000? processor block diagram" on page 11: ? changed pages (moved forward to first page of section 1.0). section 1.2 "features" on page 12: ? - modified second bullet under high-bandwidth memory buses (removed ?with nand/nor flash support?). moved what was section 1.3 ?data book notation s? in rev c to the appendix, section a.2. section 2.0 "cpu" section 2.3.2 "write buffer merging" on page 22: ? fixed addresses in the ?note? (i.e., changed 0x00010000 to 0x_0000_1000 and 0x0001002 to 0x_0000_1002). section 3.0 "memory con- trollers" section 3.1 "sdram memory controller" on page 44: ? first paragraph, removed ?(note: syncflash is not supported in early au1000 silicon. sync- flash support becomes available starting with silicon revision 2.3, also known as silicon stepping ?hc?.)? section 4.0 "dma controller" table 4-1 "dma channel base addresses" on page 73: ? corrected cell heading from kseg0 to kseg1. section 4.1.4 "dma channel buffer size registers" on page 78: ? pdf of rev c was messed up and could not be read. fixed. section 7.0 "sys- tem control" table 7-5 "gpio control registers" on page 185: ? corrected physical offset - was 0x1190 0000; changed to 0x0_1190_0000. table 7-7 "power management registers" on page 191: ? corrected physical offset - was 0x1190 0000; changed to 0x0_1190_0000.
280 amd alchemy? au1000? processor data book - preliminary appendix a: data book revision history 30360d section 8.0 "power-up, reset and boot" section 8.3 "boot" on page 198: ? corrected all references of 0x1fc0_0000 to 0x0_1fc0_0000. section 8.3.1.2 "16-bit boot for big-endian system" on page 199: ? corrected all references to 0x1fc00000 to 0x0_1fc0_0000. table a-6. edits to current revision (continued) section revisions / comments
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